mirror of https://github.com/Treeki/WindEmu.git
83 lines
3.5 KiB
C
83 lines
3.5 KiB
C
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/* Copyright (c) 2013-2014 Jeffrey Pfau
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#ifndef ISA_INLINES_H
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#define ISA_INLINES_H
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#include "macros.h"
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#include "arm.h"
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#define ARM_COND_EQ (cpu->cpsr.z)
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#define ARM_COND_NE (!cpu->cpsr.z)
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#define ARM_COND_CS (cpu->cpsr.c)
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#define ARM_COND_CC (!cpu->cpsr.c)
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#define ARM_COND_MI (cpu->cpsr.n)
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#define ARM_COND_PL (!cpu->cpsr.n)
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#define ARM_COND_VS (cpu->cpsr.v)
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#define ARM_COND_VC (!cpu->cpsr.v)
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#define ARM_COND_HI (cpu->cpsr.c && !cpu->cpsr.z)
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#define ARM_COND_LS (!cpu->cpsr.c || cpu->cpsr.z)
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#define ARM_COND_GE (!cpu->cpsr.n == !cpu->cpsr.v)
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#define ARM_COND_LT (!cpu->cpsr.n != !cpu->cpsr.v)
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#define ARM_COND_GT (!cpu->cpsr.z && !cpu->cpsr.n == !cpu->cpsr.v)
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#define ARM_COND_LE (cpu->cpsr.z || !cpu->cpsr.n != !cpu->cpsr.v)
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#define ARM_COND_AL 1
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#define ARM_SIGN(I) ((I) >> 31)
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#define ARM_SXT_8(I) (((int8_t) (I) << 24) >> 24)
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#define ARM_SXT_16(I) (((int16_t) (I) << 16) >> 16)
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#define ARM_UXT_64(I) (uint64_t)(uint32_t) (I)
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#define ARM_CARRY_FROM(M, N, D) (((uint32_t) (M) >> 31) + ((uint32_t) (N) >> 31) > ((uint32_t) (D) >> 31))
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#define ARM_BORROW_FROM(M, N, D) (((uint32_t) (M)) >= ((uint32_t) (N)))
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#define ARM_BORROW_FROM_CARRY(M, N, D, C) (ARM_UXT_64(M) >= (ARM_UXT_64(N)) + (uint64_t) (C))
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#define ARM_V_ADDITION(M, N, D) (!(ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
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#define ARM_V_SUBTRACTION(M, N, D) ((ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
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#define ARM_WAIT_MUL(R) \
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{ \
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int32_t wait; \
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if ((R & 0xFFFFFF00) == 0xFFFFFF00 || !(R & 0xFFFFFF00)) { \
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wait = 1; \
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} else if ((R & 0xFFFF0000) == 0xFFFF0000 || !(R & 0xFFFF0000)) { \
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wait = 2; \
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} else if ((R & 0xFF000000) == 0xFF000000 || !(R & 0xFF000000)) { \
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wait = 3; \
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} else { \
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wait = 4; \
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} \
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currentCycles += cpu->memory.stall(cpu, wait); \
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}
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#define ARM_STUB cpu->irqh.hitStub(cpu, opcode)
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#define ARM_ILL cpu->irqh.hitIllegal(cpu, opcode)
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static inline int32_t ARMWritePC(struct ARMCore* cpu) {
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cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -4);
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// cpu->memory.setActiveRegion(cpu, cpu->gprs[ARM_PC]);
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// LOAD_32(cpu->prefetch[0], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
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cpu->prefetch[0] = cpu->memory.load32(cpu, cpu->gprs[ARM_PC], NULL);
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cpu->gprs[ARM_PC] += 4;
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// LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
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cpu->prefetch[1] = cpu->memory.load32(cpu, cpu->gprs[ARM_PC], NULL);
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return 2 + cpu->memory.activeNonseqCycles32 + cpu->memory.activeSeqCycles32;
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}
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static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
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return mode != MODE_SYSTEM && mode != MODE_USER;
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}
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static inline void _ARMReadCPSR(struct ARMCore* cpu) {
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ARMSetPrivilegeMode(cpu, cpu->cpsr.priv);
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cpu->irqh.readCPSR(cpu);
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}
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static inline uint32_t _ARMPCAddress(struct ARMCore* cpu) {
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return cpu->gprs[ARM_PC] - 4 * 2;
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}
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#endif
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