mirror of https://github.com/Treeki/WindEmu.git
336 lines
18 KiB
C
336 lines
18 KiB
C
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/* Copyright (c) 2013-2014 Jeffrey Pfau
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#ifndef EMITTER_ARM_H
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#define EMITTER_ARM_H
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#include "emitter-inlines.h"
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#define DECLARE_INSTRUCTION_ARM(EMITTER, NAME) \
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EMITTER ## NAME
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#define DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ALU) \
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DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I)), \
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DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## I))
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#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, EX2), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, EX3), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, EX4)
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#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, NAME, P, U, W) \
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DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W)), \
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DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## I ## P ## U ## W))
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#define DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, NAME, P, U, W) \
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DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSL_ ## P ## U ## W), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _LSR_ ## P ## U ## W), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ASR_ ## P ## U ## W), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## _ROR_ ## P ## U ## W), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL)
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#define DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, NAME, MODE, W) \
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DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W)), \
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DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME ## MODE ## W))
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#define DECLARE_ARM_BRANCH_BLOCK(EMITTER, NAME) \
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DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
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// TODO: Support coprocessors
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#define DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, NAME, P, U, N, W) \
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DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME)), \
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DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
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#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2) \
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DO_8(DO_8(DO_INTERLACE(DECLARE_INSTRUCTION_ARM(EMITTER, NAME1), DECLARE_INSTRUCTION_ARM(EMITTER, NAME2))))
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#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
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DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
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#define DECLARE_ARM_EMITTER_BLOCK(EMITTER) \
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DECLARE_ARM_ALU_BLOCK(EMITTER, AND, MUL, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, ANDS, MULS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, EOR, MLA, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, EORS, MLAS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, SUB, ILL, STRHI, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, RSB, ILL, STRHI, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, RSBS, ILL, LDRHI, LDRSBI, LDRSHI), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, ADD, UMULL, STRHU, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, ADC, UMLAL, STRHU, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, ADCS, UMLALS, LDRHU, LDRSBU, LDRSHU), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, SBC, SMULL, STRHIU, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, RSC, SMLAL, STRHIU, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, RSCS, SMLALS, LDRHIU, LDRSBIU, LDRSHIU), \
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DECLARE_INSTRUCTION_ARM(EMITTER, MRS), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, SWP), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, STRHP), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
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DECLARE_INSTRUCTION_ARM(EMITTER, MSR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, BX), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, BKPT), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, STRHPW), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
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DECLARE_INSTRUCTION_ARM(EMITTER, MRSR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, SWPB), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, STRHIP), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
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DECLARE_INSTRUCTION_ARM(EMITTER, MSRR), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, STRHIPW), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_INSTRUCTION_ARM(EMITTER, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, ORR, SMLAL, STRHPU, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, MOV, SMLAL, STRHPUW, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, BIC, SMLAL, STRHIPU, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, MVN, SMLAL, STRHIPUW, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(EMITTER, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, AND), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ANDS), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EOR), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, EORS), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUB), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SUBS), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSB), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSBS), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADD), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADDS), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADC), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ADCS), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBC), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, SBCS), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSC), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, RSCS), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TST), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSR), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, TEQ), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMP), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MSRR), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, CMN), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORR), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, ORRS), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOV), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MOVS), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BIC), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, BICS), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVN), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(EMITTER, MVNS), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, , U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, , U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRT, , U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRT, , U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, , U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, , U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRBT, , U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRBT, , U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, , W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, , W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, , W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, , W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STR, P, U, W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDR, P, U, W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, ), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, STRB, P, U, W), \
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DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(EMITTER, LDRB, P, U, W), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , , ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , , ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , , ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , , ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , , ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , , ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , , ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , , ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, , U, ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, , U, ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRT, , U, ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRT, , U, ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, , U, ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, , U, ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRBT, , U, ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRBT, , U, ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, , W), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, , W), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, , W), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, , W), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STR, P, U, W), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDR, P, U, W), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, ), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, STRB, P, U, W), \
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DECLARE_ARM_LOAD_STORE_BLOCK(EMITTER, LDRB, P, U, W), \
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, ), \
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, ), \
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DA, W), \
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DA, W), \
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, ), \
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, ), \
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DA, W), \
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DA, W), \
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, ), \
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, ), \
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IA, W), \
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IA, W), \
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, ), \
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, ), \
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IA, W), \
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|
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IA, W), \
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|
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, ), \
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, ), \
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|
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, DB, W), \
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|
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DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, DB, W), \
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||
|
|
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, ), \
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||
|
|
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, ), \
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||
|
|
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, DB, W), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, DB, W), \
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||
|
|
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, ), \
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||
|
|
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, ), \
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||
|
|
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STM, IB, W), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDM, IB, W), \
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||
|
|
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, ), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, ), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, STMS, IB, W), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(EMITTER, LDMS, IB, W), \
|
||
|
|
DECLARE_ARM_BRANCH_BLOCK(EMITTER, B), \
|
||
|
|
DECLARE_ARM_BRANCH_BLOCK(EMITTER, BL), \
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|
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DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , ), \
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||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , ), \
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||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , , W), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , , W), \
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||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, ), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, ), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , , N, W), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , , N, W), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , ), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , ), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, , W), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, , W), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, ), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, ), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, , U, N, W), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, , U, N, W), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , ), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , ), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , , W), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , , W), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, ), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, ), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, , N, W), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, , N, W), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, ), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
|
||
|
|
DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
|
||
|
|
DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR), \
|
||
|
|
DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MRC), \
|
||
|
|
DECLARE_ARM_SWI_BLOCK(EMITTER)
|
||
|
|
|
||
|
|
#endif
|