mirror of https://github.com/Treeki/WindEmu.git
742 lines
31 KiB
C
742 lines
31 KiB
C
/* Copyright (c) 2013-2014 Jeffrey Pfau
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#include "isa-arm.h"
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#include "arm.h"
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#include "emitter-arm.h"
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#include "isa-inlines.h"
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#define PSR_USER_MASK 0xF0000000
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#define PSR_PRIV_MASK 0x000000CF
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#define PSR_STATE_MASK 0x00000020
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// Addressing mode 1
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static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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if (opcode & 0x00000010) {
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int rs = (opcode >> 8) & 0x0000000F;
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++cpu->cycles;
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int shift = cpu->gprs[rs];
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if (rs == ARM_PC) {
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shift += 4;
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}
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shift &= 0xFF;
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int32_t shiftVal = cpu->gprs[rm];
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if (rm == ARM_PC) {
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shiftVal += 4;
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}
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if (!shift) {
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cpu->shifterOperand = shiftVal;
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cpu->shifterCarryOut = cpu->cpsr.c;
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} else if (shift < 32) {
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cpu->shifterOperand = shiftVal << shift;
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cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
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} else if (shift == 32) {
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cpu->shifterOperand = 0;
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cpu->shifterCarryOut = shiftVal & 1;
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} else {
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cpu->shifterOperand = 0;
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cpu->shifterCarryOut = 0;
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}
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} else {
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int immediate = (opcode & 0x00000F80) >> 7;
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if (!immediate) {
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cpu->shifterOperand = cpu->gprs[rm];
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cpu->shifterCarryOut = cpu->cpsr.c;
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} else {
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cpu->shifterOperand = cpu->gprs[rm] << immediate;
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cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
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}
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}
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}
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static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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if (opcode & 0x00000010) {
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int rs = (opcode >> 8) & 0x0000000F;
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++cpu->cycles;
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int shift = cpu->gprs[rs];
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if (rs == ARM_PC) {
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shift += 4;
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}
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shift &= 0xFF;
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uint32_t shiftVal = cpu->gprs[rm];
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if (rm == ARM_PC) {
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shiftVal += 4;
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}
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if (!shift) {
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cpu->shifterOperand = shiftVal;
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cpu->shifterCarryOut = cpu->cpsr.c;
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} else if (shift < 32) {
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cpu->shifterOperand = shiftVal >> shift;
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cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
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} else if (shift == 32) {
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cpu->shifterOperand = 0;
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cpu->shifterCarryOut = shiftVal >> 31;
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} else {
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cpu->shifterOperand = 0;
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cpu->shifterCarryOut = 0;
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}
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} else {
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int immediate = (opcode & 0x00000F80) >> 7;
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if (immediate) {
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cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
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cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
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} else {
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cpu->shifterOperand = 0;
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cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
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}
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}
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}
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static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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if (opcode & 0x00000010) {
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int rs = (opcode >> 8) & 0x0000000F;
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++cpu->cycles;
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int shift = cpu->gprs[rs];
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if (rs == ARM_PC) {
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shift += 4;
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}
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shift &= 0xFF;
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int shiftVal = cpu->gprs[rm];
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if (rm == ARM_PC) {
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shiftVal += 4;
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}
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if (!shift) {
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cpu->shifterOperand = shiftVal;
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cpu->shifterCarryOut = cpu->cpsr.c;
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} else if (shift < 32) {
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cpu->shifterOperand = shiftVal >> shift;
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cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
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} else if (cpu->gprs[rm] >> 31) {
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cpu->shifterOperand = 0xFFFFFFFF;
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cpu->shifterCarryOut = 1;
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} else {
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cpu->shifterOperand = 0;
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cpu->shifterCarryOut = 0;
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}
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} else {
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int immediate = (opcode & 0x00000F80) >> 7;
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if (immediate) {
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cpu->shifterOperand = cpu->gprs[rm] >> immediate;
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cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
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} else {
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cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
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cpu->shifterOperand = cpu->shifterCarryOut;
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}
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}
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}
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static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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if (opcode & 0x00000010) {
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int rs = (opcode >> 8) & 0x0000000F;
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++cpu->cycles;
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int shift = cpu->gprs[rs];
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if (rs == ARM_PC) {
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shift += 4;
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}
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shift &= 0xFF;
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int shiftVal = cpu->gprs[rm];
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if (rm == ARM_PC) {
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shiftVal += 4;
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}
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int rotate = shift & 0x1F;
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if (!shift) {
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cpu->shifterOperand = shiftVal;
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cpu->shifterCarryOut = cpu->cpsr.c;
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} else if (rotate) {
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cpu->shifterOperand = ROR(shiftVal, rotate);
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cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
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} else {
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cpu->shifterOperand = shiftVal;
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cpu->shifterCarryOut = ARM_SIGN(shiftVal);
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}
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} else {
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int immediate = (opcode & 0x00000F80) >> 7;
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if (immediate) {
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cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
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cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
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} else {
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// RRX
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cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
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cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
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}
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}
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}
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static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
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int rotate = (opcode & 0x00000F00) >> 7;
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int immediate = opcode & 0x000000FF;
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if (!rotate) {
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cpu->shifterOperand = immediate;
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cpu->shifterCarryOut = cpu->cpsr.c;
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} else {
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cpu->shifterOperand = ROR(immediate, rotate);
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cpu->shifterCarryOut = ARM_SIGN(cpu->shifterOperand);
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}
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}
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// Instruction definitions
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// Beware pre-processor antics
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ATTRIBUTE_NOINLINE static void _additionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
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cpu->cpsr.flags = 0;
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cpu->cpsr.n = ARM_SIGN(d);
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cpu->cpsr.z = !d;
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cpu->cpsr.c = ARM_CARRY_FROM(m, n, d);
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cpu->cpsr.v = ARM_V_ADDITION(m, n, d);
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}
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ATTRIBUTE_NOINLINE static void _subtractionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
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cpu->cpsr.flags = 0;
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cpu->cpsr.n = ARM_SIGN(d);
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cpu->cpsr.z = !d;
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cpu->cpsr.c = ARM_BORROW_FROM(m, n, d);
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cpu->cpsr.v = ARM_V_SUBTRACTION(m, n, d);
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}
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ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int32_t d) {
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cpu->cpsr.n = ARM_SIGN(d);
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cpu->cpsr.z = !d; \
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cpu->cpsr.c = cpu->shifterCarryOut; \
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}
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#define ARM_ADDITION_S(M, N, D) \
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if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
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cpu->cpsr = cpu->spsr; \
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_ARMReadCPSR(cpu); \
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} else { \
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_additionS(cpu, M, N, D); \
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}
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#define ARM_SUBTRACTION_S(M, N, D) \
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if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
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cpu->cpsr = cpu->spsr; \
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_ARMReadCPSR(cpu); \
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} else { \
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_subtractionS(cpu, M, N, D); \
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}
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#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
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if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
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cpu->cpsr = cpu->spsr; \
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_ARMReadCPSR(cpu); \
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} else { \
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cpu->cpsr.n = ARM_SIGN(D); \
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cpu->cpsr.z = !(D); \
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cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
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cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
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}
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#define ARM_NEUTRAL_S(M, N, D) \
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if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
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cpu->cpsr = cpu->spsr; \
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_ARMReadCPSR(cpu); \
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} else { \
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_neutralS(cpu, D); \
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}
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#define ARM_NEUTRAL_HI_S(DLO, DHI) \
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cpu->cpsr.n = ARM_SIGN(DHI); \
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cpu->cpsr.z = !((DHI) | (DLO));
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#define ADDR_MODE_2_I_TEST (opcode & 0x00000F80)
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#define ADDR_MODE_2_I ((opcode & 0x00000F80) >> 7)
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#define ADDR_MODE_2_ADDRESS (address)
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#define ADDR_MODE_2_RN (cpu->gprs[rn])
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#define ADDR_MODE_2_RM (cpu->gprs[rm])
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#define ADDR_MODE_2_IMMEDIATE (opcode & 0x00000FFF)
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#define ADDR_MODE_2_INDEX(U_OP, M) (cpu->gprs[rn] U_OP M)
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#define ADDR_MODE_2_WRITEBACK(ADDR) \
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cpu->gprs[rn] = ADDR; \
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if (UNLIKELY(rn == ARM_PC)) { \
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currentCycles += ARMWritePC(cpu); \
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}
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#define ADDR_MODE_2_WRITEBACK_PRE_STORE(WB)
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#define ADDR_MODE_2_WRITEBACK_POST_STORE(WB) WB
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#define ADDR_MODE_2_WRITEBACK_PRE_LOAD(WB) WB
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#define ADDR_MODE_2_WRITEBACK_POST_LOAD(WB)
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#define ADDR_MODE_2_LSL (cpu->gprs[rm] << ADDR_MODE_2_I)
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#define ADDR_MODE_2_LSR (ADDR_MODE_2_I_TEST ? ((uint32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : 0)
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#define ADDR_MODE_2_ASR (ADDR_MODE_2_I_TEST ? ((int32_t) cpu->gprs[rm]) >> ADDR_MODE_2_I : ((int32_t) cpu->gprs[rm]) >> 31)
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#define ADDR_MODE_2_ROR (ADDR_MODE_2_I_TEST ? ROR(cpu->gprs[rm], ADDR_MODE_2_I) : (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1))
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#define ADDR_MODE_3_ADDRESS ADDR_MODE_2_ADDRESS
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#define ADDR_MODE_3_RN ADDR_MODE_2_RN
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#define ADDR_MODE_3_RM ADDR_MODE_2_RM
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#define ADDR_MODE_3_IMMEDIATE (((opcode & 0x00000F00) >> 4) | (opcode & 0x0000000F))
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#define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M)
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#define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR)
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#define ADDR_MODE_4_WRITEBACK_LDM \
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if (!((1 << rn) & rs)) { \
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cpu->gprs[rn] = address; \
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}
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#define ADDR_MODE_4_WRITEBACK_STM cpu->gprs[rn] = address;
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#define ARM_LOAD_POST_BODY \
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currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32; \
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if (rd == ARM_PC) { \
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currentCycles += ARMWritePC(cpu); \
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}
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#define ARM_STORE_POST_BODY \
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currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
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#define DEFINE_INSTRUCTION_ARM(NAME, BODY) \
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static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \
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int currentCycles = ARM_PREFETCH_CYCLES; \
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BODY; \
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cpu->cycles += currentCycles; \
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}
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#define DEFINE_ALU_INSTRUCTION_EX_ARM(NAME, S_BODY, SHIFTER, BODY) \
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DEFINE_INSTRUCTION_ARM(NAME, \
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int rd = (opcode >> 12) & 0xF; \
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int rn = (opcode >> 16) & 0xF; \
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UNUSED(rn); \
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SHIFTER(cpu, opcode); \
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BODY; \
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S_BODY; \
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if (rd == ARM_PC) { \
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currentCycles += ARMWritePC(cpu); \
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})
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#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
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#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
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#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
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DEFINE_INSTRUCTION_ARM(NAME, \
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int rd = (opcode >> 16) & 0xF; \
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int rs = (opcode >> 8) & 0xF; \
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int rm = opcode & 0xF; \
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if (rd == ARM_PC) { \
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return; \
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} \
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ARM_WAIT_MUL(cpu->gprs[rs]); \
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BODY; \
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S_BODY; \
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currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
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#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
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DEFINE_INSTRUCTION_ARM(NAME, \
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int rd = (opcode >> 12) & 0xF; \
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int rdHi = (opcode >> 16) & 0xF; \
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int rs = (opcode >> 8) & 0xF; \
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int rm = opcode & 0xF; \
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if (rdHi == ARM_PC || rd == ARM_PC) { \
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return; \
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} \
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currentCycles += cpu->memory.stall(cpu, WAIT); \
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BODY; \
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S_BODY; \
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currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
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#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
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DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
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DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
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#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
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DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
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DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
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#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, LS, BODY) \
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DEFINE_INSTRUCTION_ARM(NAME, \
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uint32_t address; \
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int rn = (opcode >> 16) & 0xF; \
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int rd = (opcode >> 12) & 0xF; \
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int rm = opcode & 0xF; \
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UNUSED(rm); \
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address = ADDRESS; \
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ADDR_MODE_2_WRITEBACK_PRE_ ## LS (WRITEBACK); \
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BODY; \
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ADDR_MODE_2_WRITEBACK_POST_ ## LS (WRITEBACK);)
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#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, LS, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, SHIFTER)), LS, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, SHIFTER)), LS, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER), , LS, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER), , LS, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY)
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#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, LS, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, LS, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, LS, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), , LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), LS, BODY) \
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|
|
|
#define DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(NAME, LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM)), LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM)), LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), , LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), , LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_RM), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE)), LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_3_RN, ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE)), LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), , LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPW, ADDR_MODE_3_INDEX(-, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPU, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), , LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IPUW, ADDR_MODE_3_INDEX(+, ADDR_MODE_3_IMMEDIATE), ADDR_MODE_3_WRITEBACK(ADDR_MODE_3_ADDRESS), LS, BODY) \
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|
|
|
#define DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), LS, BODY) \
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|
|
|
#define DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(NAME, LS, BODY) \
|
|
DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, LS, BODY) \
|
|
DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, LS, BODY) \
|
|
DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, LS, BODY) \
|
|
DEFINE_LOAD_STORE_T_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
|
|
DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), LS, BODY) \
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|
|
|
#define ARM_MS_PRE(IS_LOAD) \
|
|
enum PrivilegeMode privilegeMode = cpu->privilegeMode; \
|
|
if (!(opcode & 0x8000) || !IS_LOAD) ARMSetPrivilegeMode(cpu, MODE_USER);
|
|
|
|
#define ARM_MS_POST(IS_LOAD) \
|
|
ARMSetPrivilegeMode(cpu, privilegeMode); \
|
|
if (IS_LOAD && (opcode & 0x8000)) { \
|
|
cpu->cpsr.packed = cpu->spsr.packed;\
|
|
ARMSetPrivilegeMode(cpu, cpu->cpsr.priv);\
|
|
}
|
|
|
|
#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, LS, WRITEBACK, S_PRE, S_POST, DIRECTION, POST_BODY) \
|
|
DEFINE_INSTRUCTION_ARM(NAME, \
|
|
int rn = (opcode >> 16) & 0xF; \
|
|
int rs = opcode & 0x0000FFFF; \
|
|
uint32_t address = cpu->gprs[rn]; \
|
|
S_PRE; \
|
|
address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
|
|
POST_BODY; \
|
|
WRITEBACK; \
|
|
S_POST; \
|
|
)
|
|
|
|
|
|
#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, LS, IS_LOAD, POST_BODY) \
|
|
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, LS, , , , DA, POST_BODY) \
|
|
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DA, POST_BODY) \
|
|
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DB, LS, , , , DB, POST_BODY) \
|
|
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , DB, POST_BODY) \
|
|
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IA, LS, , , , IA, POST_BODY) \
|
|
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IA, POST_BODY) \
|
|
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IB, LS, , , , IB, POST_BODY) \
|
|
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## IBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, , , IB, POST_BODY) \
|
|
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDA, LS, , ARM_MS_PRE(IS_LOAD), ARM_MS_POST(IS_LOAD), DA, POST_BODY) \
|
|
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE(IS_LOAD), ARM_MS_POST(IS_LOAD), DA, POST_BODY) \
|
|
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDB, LS, , ARM_MS_PRE(IS_LOAD), ARM_MS_POST(IS_LOAD), DB, POST_BODY) \
|
|
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SDBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE(IS_LOAD), ARM_MS_POST(IS_LOAD), DB, POST_BODY) \
|
|
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIA, LS, , ARM_MS_PRE(IS_LOAD), ARM_MS_POST(IS_LOAD), IA, POST_BODY) \
|
|
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIAW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE(IS_LOAD), ARM_MS_POST(IS_LOAD), IA, POST_BODY) \
|
|
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIB, LS, , ARM_MS_PRE(IS_LOAD), ARM_MS_POST(IS_LOAD), IB, POST_BODY) \
|
|
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## SIBW, LS, ADDR_MODE_4_WRITEBACK_ ## NAME, ARM_MS_PRE(IS_LOAD), ARM_MS_POST(IS_LOAD), IB, POST_BODY)
|
|
|
|
// Begin ALU definitions
|
|
|
|
DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
|
|
int32_t n = cpu->gprs[rn];
|
|
cpu->gprs[rd] = n + cpu->shifterOperand;)
|
|
|
|
DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
|
|
int32_t n = cpu->gprs[rn];
|
|
cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
|
|
|
|
DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
|
|
cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;)
|
|
|
|
DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
|
|
cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;)
|
|
|
|
DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
|
|
int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;)
|
|
|
|
DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
|
|
int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;)
|
|
|
|
DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
|
|
cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;)
|
|
|
|
DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
|
|
cpu->gprs[rd] = cpu->shifterOperand;)
|
|
|
|
DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
|
|
cpu->gprs[rd] = ~cpu->shifterOperand;)
|
|
|
|
DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
|
|
cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;)
|
|
|
|
DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
|
|
int32_t n = cpu->gprs[rn];
|
|
cpu->gprs[rd] = cpu->shifterOperand - n;)
|
|
|
|
DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
|
|
int32_t n = cpu->gprs[rn];
|
|
cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
|
|
|
|
DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
|
|
int32_t n = cpu->gprs[rn];
|
|
cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
|
|
|
|
DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
|
|
int32_t n = cpu->gprs[rn];
|
|
cpu->gprs[rd] = n - cpu->shifterOperand;)
|
|
|
|
DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
|
|
int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;)
|
|
|
|
DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
|
|
int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;)
|
|
|
|
// End ALU definitions
|
|
|
|
// Begin multiply definitions
|
|
|
|
DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
|
|
DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
|
|
|
|
DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
|
|
int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
|
|
int32_t dm = cpu->gprs[rd];
|
|
int32_t dn = d;
|
|
cpu->gprs[rd] = dm + dn;
|
|
cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
|
|
ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
|
|
|
|
DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
|
|
int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
|
|
cpu->gprs[rd] = d;
|
|
cpu->gprs[rdHi] = d >> 32;,
|
|
ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
|
|
|
|
DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
|
|
uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
|
|
int32_t dm = cpu->gprs[rd];
|
|
int32_t dn = d;
|
|
cpu->gprs[rd] = dm + dn;
|
|
cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
|
|
ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
|
|
|
|
DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
|
|
uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
|
|
cpu->gprs[rd] = d;
|
|
cpu->gprs[rdHi] = d >> 32;,
|
|
ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
|
|
|
|
// End multiply definitions
|
|
|
|
// Begin load/store definitions
|
|
|
|
DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, LOAD, cpu->gprs[rd] = cpu->memory.load32(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
|
|
DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, LOAD, cpu->gprs[rd] = cpu->memory.load8(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
|
|
DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, LOAD, cpu->gprs[rd] = cpu->memory.load16(cpu, address, ¤tCycles); ARM_LOAD_POST_BODY;)
|
|
DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, LOAD, cpu->gprs[rd] = ARM_SXT_8(cpu->memory.load8(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
|
|
DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, LOAD, cpu->gprs[rd] = address & 1 ? ARM_SXT_8(cpu->memory.load16(cpu, address, ¤tCycles)) : ARM_SXT_16(cpu->memory.load16(cpu, address, ¤tCycles)); ARM_LOAD_POST_BODY;)
|
|
DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, STORE, cpu->memory.store32(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
|
|
DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, STORE, cpu->memory.store8(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
|
|
DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, STORE, cpu->memory.store16(cpu, address, cpu->gprs[rd], ¤tCycles); ARM_STORE_POST_BODY;)
|
|
|
|
DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT, LOAD,
|
|
enum PrivilegeMode priv = cpu->privilegeMode;
|
|
ARMSetPrivilegeMode(cpu, MODE_USER);
|
|
int32_t r = cpu->memory.load8(cpu, address, ¤tCycles);
|
|
ARMSetPrivilegeMode(cpu, priv);
|
|
cpu->gprs[rd] = r;
|
|
ARM_LOAD_POST_BODY;)
|
|
|
|
DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT, LOAD,
|
|
enum PrivilegeMode priv = cpu->privilegeMode;
|
|
ARMSetPrivilegeMode(cpu, MODE_USER);
|
|
int32_t r = cpu->memory.load32(cpu, address, ¤tCycles);
|
|
ARMSetPrivilegeMode(cpu, priv);
|
|
cpu->gprs[rd] = r;
|
|
ARM_LOAD_POST_BODY;)
|
|
|
|
DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT, STORE,
|
|
enum PrivilegeMode priv = cpu->privilegeMode;
|
|
int32_t r = cpu->gprs[rd];
|
|
ARMSetPrivilegeMode(cpu, MODE_USER);
|
|
cpu->memory.store8(cpu, address, r, ¤tCycles);
|
|
ARMSetPrivilegeMode(cpu, priv);
|
|
ARM_STORE_POST_BODY;)
|
|
|
|
DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT, STORE,
|
|
enum PrivilegeMode priv = cpu->privilegeMode;
|
|
int32_t r = cpu->gprs[rd];
|
|
ARMSetPrivilegeMode(cpu, MODE_USER);
|
|
cpu->memory.store32(cpu, address, r, ¤tCycles);
|
|
ARMSetPrivilegeMode(cpu, priv);
|
|
ARM_STORE_POST_BODY;)
|
|
|
|
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM,
|
|
load, true,
|
|
currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32;
|
|
if ((rs & 0x8000) || !rs) {
|
|
currentCycles += ARMWritePC(cpu);
|
|
})
|
|
|
|
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM,
|
|
store, false,
|
|
ARM_STORE_POST_BODY;)
|
|
|
|
DEFINE_INSTRUCTION_ARM(SWP,
|
|
int rm = opcode & 0xF;
|
|
int rd = (opcode >> 12) & 0xF;
|
|
int rn = (opcode >> 16) & 0xF;
|
|
int32_t d = cpu->memory.load32(cpu, cpu->gprs[rn], ¤tCycles);
|
|
cpu->memory.store32(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
|
|
cpu->gprs[rd] = d;)
|
|
|
|
DEFINE_INSTRUCTION_ARM(SWPB,
|
|
int rm = opcode & 0xF;
|
|
int rd = (opcode >> 12) & 0xF;
|
|
int rn = (opcode >> 16) & 0xF;
|
|
int32_t d = cpu->memory.load8(cpu, cpu->gprs[rn], ¤tCycles);
|
|
cpu->memory.store8(cpu, cpu->gprs[rn], cpu->gprs[rm], ¤tCycles);
|
|
cpu->gprs[rd] = d;)
|
|
|
|
// End load/store definitions
|
|
|
|
// Begin branch definitions
|
|
|
|
DEFINE_INSTRUCTION_ARM(B,
|
|
int32_t offset = opcode << 8;
|
|
offset >>= 6;
|
|
cpu->gprs[ARM_PC] += offset;
|
|
currentCycles += ARMWritePC(cpu);)
|
|
|
|
DEFINE_INSTRUCTION_ARM(BL,
|
|
int32_t immediate = (opcode & 0x00FFFFFF) << 8;
|
|
cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] - 4;
|
|
cpu->gprs[ARM_PC] += immediate >> 6;
|
|
currentCycles += ARMWritePC(cpu);)
|
|
|
|
DEFINE_INSTRUCTION_ARM(BX,
|
|
int rm = opcode & 0x0000000F;
|
|
cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
|
|
currentCycles += ARMWritePC(cpu);
|
|
)
|
|
|
|
// End branch definitions
|
|
|
|
// Begin coprocessor definitions
|
|
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DEFINE_INSTRUCTION_ARM(CDP, ARM_STUB)
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DEFINE_INSTRUCTION_ARM(LDC, ARM_STUB)
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DEFINE_INSTRUCTION_ARM(STC, ARM_STUB)
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DEFINE_INSTRUCTION_ARM(MCR, ARM_STUB)
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DEFINE_INSTRUCTION_ARM(MRC, ARM_STUB)
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// Begin miscellaneous definitions
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DEFINE_INSTRUCTION_ARM(BKPT, cpu->irqh.bkpt32(cpu, ((opcode >> 4) & 0xFFF0) | (opcode & 0xF))); // Not strictly in ARMv4T, but here for convenience
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DEFINE_INSTRUCTION_ARM(ILL, ARM_ILL) // Illegal opcode
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DEFINE_INSTRUCTION_ARM(MSR,
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int c = opcode & 0x00010000;
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int f = opcode & 0x00080000;
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int32_t operand = cpu->gprs[opcode & 0x0000000F];
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int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
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if (mask & PSR_USER_MASK) {
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cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
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}
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if (mask & PSR_STATE_MASK) {
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cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
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}
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if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
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ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
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cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
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}
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_ARMReadCPSR(cpu);
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// LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - 4) & cpu->memory.activeMask, cpu->memory.activeRegion);
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// LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
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cpu->prefetch[0] = cpu->memory.load32(cpu, cpu->gprs[ARM_PC] - 4, NULL);
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cpu->prefetch[1] = cpu->memory.load32(cpu, cpu->gprs[ARM_PC], NULL);
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)
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DEFINE_INSTRUCTION_ARM(MSRR,
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int c = opcode & 0x00010000;
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int f = opcode & 0x00080000;
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int32_t operand = cpu->gprs[opcode & 0x0000000F];
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int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
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mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
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cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
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DEFINE_INSTRUCTION_ARM(MRS, \
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int rd = (opcode >> 12) & 0xF; \
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cpu->gprs[rd] = cpu->cpsr.packed;)
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DEFINE_INSTRUCTION_ARM(MRSR, \
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int rd = (opcode >> 12) & 0xF; \
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cpu->gprs[rd] = cpu->spsr.packed;)
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DEFINE_INSTRUCTION_ARM(MSRI,
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int c = opcode & 0x00010000;
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int f = opcode & 0x00080000;
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int rotate = (opcode & 0x00000F00) >> 7;
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int32_t operand = ROR(opcode & 0x000000FF, rotate);
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int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
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if (mask & PSR_USER_MASK) {
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cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
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}
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if (mask & PSR_STATE_MASK) {
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cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_STATE_MASK) | (operand & PSR_STATE_MASK);
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}
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if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
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ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
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cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
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}
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_ARMReadCPSR(cpu);
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// LOAD_32(cpu->prefetch[0], (cpu->gprs[ARM_PC] - 4) & cpu->memory.activeMask, cpu->memory.activeRegion);
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// LOAD_32(cpu->prefetch[1], cpu->gprs[ARM_PC] & cpu->memory.activeMask, cpu->memory.activeRegion);
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cpu->prefetch[0] = cpu->memory.load32(cpu, cpu->gprs[ARM_PC] - 4, NULL);
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cpu->prefetch[1] = cpu->memory.load32(cpu, cpu->gprs[ARM_PC], NULL);
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)
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DEFINE_INSTRUCTION_ARM(MSRRI,
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int c = opcode & 0x00010000;
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int f = opcode & 0x00080000;
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int rotate = (opcode & 0x00000F00) >> 7;
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int32_t operand = ROR(opcode & 0x000000FF, rotate);
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int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
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mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
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cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask) | 0x00000010;)
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DEFINE_INSTRUCTION_ARM(SWI, cpu->irqh.swi32(cpu, opcode & 0xFFFFFF))
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const ARMInstruction _armTable[0x1000] = {
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DECLARE_ARM_EMITTER_BLOCK(_ARMInstruction)
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};
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