mirror of https://github.com/Treeki/WindEmu.git
175 lines
3.8 KiB
C
175 lines
3.8 KiB
C
/* Copyright (c) 2013-2014 Jeffrey Pfau
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#ifndef ARM_H
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#define ARM_H
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#include "common.h"
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CXX_GUARD_START
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// #include <mgba/core/cpu.h>
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enum {
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ARM_SP = 13,
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ARM_LR = 14,
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ARM_PC = 15
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};
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enum PrivilegeMode {
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MODE_USER = 0x10,
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MODE_FIQ = 0x11,
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MODE_IRQ = 0x12,
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MODE_SUPERVISOR = 0x13,
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MODE_ABORT = 0x17,
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MODE_UNDEFINED = 0x1B,
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MODE_SYSTEM = 0x1F
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};
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enum ExecutionVector {
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BASE_RESET = 0x00000000,
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BASE_UNDEF = 0x00000004,
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BASE_SWI = 0x00000008,
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BASE_PABT = 0x0000000C,
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BASE_DABT = 0x00000010,
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BASE_IRQ = 0x00000018,
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BASE_FIQ = 0x0000001C
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};
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enum RegisterBank {
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BANK_NONE = 0,
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BANK_FIQ = 1,
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BANK_IRQ = 2,
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BANK_SUPERVISOR = 3,
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BANK_ABORT = 4,
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BANK_UNDEFINED = 5
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};
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enum LSMDirection {
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LSM_B = 1,
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LSM_D = 2,
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LSM_IA = 0,
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LSM_IB = 1,
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LSM_DA = 2,
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LSM_DB = 3
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};
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struct ARMCore;
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union PSR {
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struct {
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#if defined(__POWERPC__) || defined(__PPC__)
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unsigned n : 1;
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unsigned z : 1;
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unsigned c : 1;
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unsigned v : 1;
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unsigned unused : 20;
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unsigned i : 1;
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unsigned f : 1;
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unsigned t : 1;
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unsigned priv : 5;
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#else
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unsigned priv : 5;
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unsigned t : 1;
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unsigned f : 1;
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unsigned i : 1;
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unsigned unused : 20;
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unsigned v : 1;
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unsigned c : 1;
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unsigned z : 1;
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unsigned n : 1;
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#endif
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};
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struct {
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#if defined(__BIG_ENDIAN__)
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uint8_t flags;
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uint8_t status;
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uint8_t extension;
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uint8_t control;
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#else
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uint8_t control;
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uint8_t extension;
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uint8_t status;
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uint8_t flags;
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#endif
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};
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int32_t packed;
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};
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struct ARMMemory {
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uint32_t (*load32)(struct ARMCore*, uint32_t address, int* cycleCounter);
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uint32_t (*load16)(struct ARMCore*, uint32_t address, int* cycleCounter);
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uint32_t (*load8)(struct ARMCore*, uint32_t address, int* cycleCounter);
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void (*store32)(struct ARMCore*, uint32_t address, int32_t value, int* cycleCounter);
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void (*store16)(struct ARMCore*, uint32_t address, int16_t value, int* cycleCounter);
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void (*store8)(struct ARMCore*, uint32_t address, int8_t value, int* cycleCounter);
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uint32_t (*loadMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
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int* cycleCounter);
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uint32_t (*storeMultiple)(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
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int* cycleCounter);
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uint32_t activeSeqCycles32;
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// uint32_t activeSeqCycles16;
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uint32_t activeNonseqCycles32;
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// uint32_t activeNonseqCycles16;
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int32_t (*stall)(struct ARMCore*, int32_t wait);
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};
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struct ARMInterruptHandler {
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void (*reset)(struct ARMCore* cpu);
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void (*processEvents)(struct ARMCore* cpu);
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// void (*swi16)(struct ARMCore* cpu, int immediate);
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void (*swi32)(struct ARMCore* cpu, int immediate);
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void (*hitIllegal)(struct ARMCore* cpu, uint32_t opcode);
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// void (*bkpt16)(struct ARMCore* cpu, int immediate);
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void (*bkpt32)(struct ARMCore* cpu, int immediate);
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void (*readCPSR)(struct ARMCore* cpu);
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void (*hitStub)(struct ARMCore* cpu, uint32_t opcode);
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};
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struct ARMCore {
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int32_t gprs[16];
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union PSR cpsr;
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union PSR spsr;
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int64_t cycles;
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int64_t nextEvent;
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int halted;
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int32_t bankedRegisters[6][7];
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int32_t bankedSPSRs[6];
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int32_t shifterOperand;
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int32_t shifterCarryOut;
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uint32_t prefetch[2];
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enum PrivilegeMode privilegeMode;
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struct ARMMemory memory;
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struct ARMInterruptHandler irqh;
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void *owner;
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};
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void ARMReset(struct ARMCore* cpu);
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void ARMSetPrivilegeMode(struct ARMCore*, enum PrivilegeMode);
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void ARMRaiseIRQ(struct ARMCore*);
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void ARMRaiseFIQ(struct ARMCore*);
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void ARMRaiseSWI(struct ARMCore*);
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void ARMRaiseUndefined(struct ARMCore*);
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void ARMRun(struct ARMCore* cpu);
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void ARMRunLoop(struct ARMCore* cpu);
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void ARMRunFake(struct ARMCore* cpu, uint32_t opcode);
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CXX_GUARD_END
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#endif
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