mirror of https://github.com/Treeki/WindEmu.git
274 lines
8.4 KiB
C++
274 lines
8.4 KiB
C++
#pragma once
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#include <stdint.h>
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#include <optional>
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#include <variant>
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using namespace std;
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// ASSUMPTIONS:
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// - Little-endian will be used
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// - 26-bit address spaces will not be used
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// - Alignment faults will always be on
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// Write buffer is 4 address FIFO, 8 data FIFO
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// TLB is 64 entries
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typedef optional<uint32_t> MaybeU32;
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class ARM710a
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{
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public:
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void test();
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enum ValueSize { V8 = 0, V32 = 1 };
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enum MMUFault : uint64_t {
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// ref: datasheet 9-13 (p111)
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NoFault = 0,
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AlignmentFault = 1,
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// the ARM gods say there is to be no fault 2 or 3
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SectionLinefetchError = 4,
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SectionTranslationFault = 5,
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PageLinefetchError = 6,
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PageTranslationFault = 7,
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SectionOtherBusError = 8,
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SectionDomainFault = 9,
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PageOtherBusError = 0xA,
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PageDomainFault = 0xB,
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Lv1TranslationError = 0xC,
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SectionPermissionFault = 0xD,
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Lv2TranslationError = 0xE,
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PagePermissionFault = 0xF,
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// not actually in the ARM datasheet
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// so we are reusing it for nefarious purposes
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NonMMUError = 3,
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MMUFaultTypeMask = 0xF,
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MMUFaultDomainMask = 0xF0,
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MMUFaultDomainShift = 4,
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MMUFaultAddressMask = 0xFFFFFFFF00000000,
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MMUFaultAddressShift = 32
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};
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ARM710a() {
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cp15_id = 0x41047100;
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clearAllValues();
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}
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virtual ~ARM710a() { }
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void clearAllValues() {
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bank = MainBank;
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CPSR = 0;
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for (int i = 0; i < 16; i++) GPRs[i] = 0;
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for (int i = 0; i < 5; i++) {
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fiqBankedRegisters[0][i] = 0;
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fiqBankedRegisters[1][i] = 0;
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SPSRs[i] = 0;
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}
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for (int i = 0; i < 6; i++) {
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allModesBankedRegisters[i][0] = 0;
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allModesBankedRegisters[i][1] = 0;
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}
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cp15_control = 0;
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cp15_translationTableBase = 0;
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cp15_domainAccessControl = 0;
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cp15_faultStatus = 0;
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cp15_faultAddress = 0;
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prefetchCount = 0;
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clearCache();
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flushTlb();
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}
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void setProcessorID(uint32_t v) { cp15_id = v; }
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void requestFIQ(); // pull nFIQ low
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void requestIRQ(); // pull nIRQ low
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void reset(); // pull nRESET low
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bool instructionReady() const { return (prefetchCount == 2); }
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uint32_t tick(); // run the chip for at least 1 clock cycle
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MaybeU32 readVirtualDebug(uint32_t virtAddr, ValueSize valueSize);
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MaybeU32 virtToPhys(uint32_t virtAddr);
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pair<MaybeU32, MMUFault> readVirtual(uint32_t virtAddr, ValueSize valueSize);
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virtual MaybeU32 readPhysical(uint32_t physAddr, ValueSize valueSize) = 0;
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MMUFault writeVirtual(uint32_t value, uint32_t virtAddr, ARM710a::ValueSize valueSize);
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virtual bool writePhysical(uint32_t value, uint32_t physAddr, ARM710a::ValueSize valueSize) = 0;
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uint32_t getGPR(int index) const { return GPRs[index]; }
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uint32_t getCPSR() const { return CPSR; }
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void setLogger(std::function<void(const char *)> newLogger) { logger = newLogger; }
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protected:
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void log(const char *format, ...);
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private:
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std::function<void(const char *)> logger;
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enum { Nop = 0xE1A00000 };
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enum Mode : uint8_t {
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User32 = 0x10,
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FIQ32 = 0x11,
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IRQ32 = 0x12,
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Supervisor32 = 0x13,
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Abort32 = 0x17,
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Undefined32 = 0x1B
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};
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enum BankIndex : uint8_t {
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FiqBank,
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IrqBank,
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SvcBank,
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AbtBank,
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UndBank,
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MainBank
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};
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constexpr static const BankIndex modeToBank[16] = {
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MainBank, FiqBank, IrqBank, SvcBank,
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MainBank, MainBank, MainBank, AbtBank,
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MainBank, MainBank, MainBank, UndBank,
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MainBank, MainBank, MainBank, MainBank
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};
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enum : uint32_t {
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CPSR_ModeMask = 0x0000001F,
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CPSR_FIQDisable = 0x00000040,
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CPSR_IRQDisable = 0x00000080,
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CPSR_V = 0x10000000,
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CPSR_C = 0x20000000,
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CPSR_Z = 0x40000000,
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CPSR_N = 0x80000000,
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CPSR_FlagMask = 0xF0000000
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};
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// active state
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BankIndex bank;
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uint32_t CPSR;
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uint32_t GPRs[16];
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// saved state
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uint32_t fiqBankedRegisters[2][5]; // R8..R12 inclusive
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uint32_t allModesBankedRegisters[6][2]; // R13, R14
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uint32_t SPSRs[5];
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// coprocessor 15
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uint32_t cp15_id; // 0: read-only
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uint32_t cp15_control; // 1: write-only
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uint32_t cp15_translationTableBase; // 2: write-only
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uint32_t cp15_domainAccessControl; // 3: write-only
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uint8_t cp15_faultStatus; // 5: read-only (writing has unrelated effects)
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uint32_t cp15_faultAddress; // 6: read-only (writing has unrelated effects)
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bool flagV() const { return CPSR & CPSR_V; }
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bool flagC() const { return CPSR & CPSR_C; }
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bool flagZ() const { return CPSR & CPSR_Z; }
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bool flagN() const { return CPSR & CPSR_N; }
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bool checkCondition(int cond) const {
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switch (cond) {
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/*EQ*/ case 0: return flagZ();
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/*NE*/ case 1: return !flagZ();
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/*CS*/ case 2: return flagC();
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/*CC*/ case 3: return !flagC();
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/*MI*/ case 4: return flagN();
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/*PL*/ case 5: return !flagN();
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/*VS*/ case 6: return flagV();
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/*VC*/ case 7: return !flagV();
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/*HI*/ case 8: return flagC() && !flagZ();
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/*LS*/ case 9: return !flagC() || flagZ();
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/*GE*/ case 0xA: return flagN() == flagV();
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/*LT*/ case 0xB: return flagN() != flagV();
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/*GT*/ case 0xC: return !flagZ() && (flagN() == flagV());
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/*LE*/ case 0xD: return flagZ() || (flagN() != flagV());
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/*AL*/ case 0xE: return true;
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/*NV*/ /*case 0xF:*/
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default: return false;
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}
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}
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static Mode modeFromCPSR(uint32_t v) { return (Mode)(v & CPSR_ModeMask); }
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Mode currentMode() const { return modeFromCPSR(CPSR); }
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BankIndex currentBank() const { return modeToBank[(Mode)(CPSR & 0xF)]; }
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bool isPrivileged() const { return (CPSR & 0x1F) > User32; }
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bool isMMUEnabled() const { return (cp15_control & 1); }
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bool isAlignmentFaultEnabled() const { return (cp15_control & 2); }
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bool isCacheEnabled() const { return (cp15_control & 4); }
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bool isWriteBufferEnabled() const { return (cp15_control & 8); }
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void switchMode(Mode mode);
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void switchBank(BankIndex bank);
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void raiseException(Mode mode, uint32_t savedPC, uint32_t newPC);
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// MMU/TLB
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enum MMUFaultSorP : uint64_t {
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SorPLinefetchError = 4,
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SorPTranslationFault = 5,
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SorPOtherBusError = 8,
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SorPDomainFault = 9,
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SorPPermissionFault = 0xD,
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};
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MMUFault encodeFault(MMUFault fault, int domain, uint32_t virtAddr) const {
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return (MMUFault)(fault | (domain << 4) | ((uint64_t)virtAddr << 32));
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}
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MMUFault encodeFaultSorP(MMUFaultSorP baseFault, bool isPage, int domain, uint32_t virtAddr) const {
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return (MMUFault)(baseFault | (isPage ? 2 : 0) | (domain << 4) | ((uint64_t)virtAddr << 32));
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}
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enum { TlbSize = 64 };
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struct TlbEntry { uint32_t addrMask, addr, lv1Entry, lv2Entry; };
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TlbEntry tlb[TlbSize];
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int nextTlbIndex = 0;
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void flushTlb();
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void flushTlb(uint32_t virtAddr);
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variant<TlbEntry *, MMUFault> translateAddressUsingTlb(uint32_t virtAddr, TlbEntry *useMe=nullptr);
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TlbEntry *_allocateTlbEntry(uint32_t addrMask, uint32_t addr);
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static uint32_t physAddrFromTlbEntry(TlbEntry *tlbEntry, uint32_t virtAddr);
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MMUFault checkAccessPermissions(TlbEntry *entry, uint32_t virtAddr, bool isWrite) const;
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bool faultTriggeredThisCycle = false;
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void reportFault(MMUFault fault);
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// Instruction/Data Cache
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enum {
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CacheSets = 4,
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CacheBlocksPerSet = 128,
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CacheBlockSize = 0x10,
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CacheAddressLineMask = 0x0000000F,
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CacheAddressSetMask = 0x00000030, CacheAddressSetShift = 4,
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CacheAddressTagMask = 0xFFFFFFC0,
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CacheBlockEnabled = 1
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};
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uint32_t cacheBlockTags[CacheSets][CacheBlocksPerSet];
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uint8_t cacheBlocks[CacheSets][CacheBlocksPerSet][CacheBlockSize];
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void clearCache();
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uint8_t *findCacheLine(uint32_t virtAddr);
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pair<MaybeU32, MMUFault> addCacheLineAndRead(uint32_t physAddr, uint32_t virtAddr, ValueSize valueSize, int domain, bool isPage);
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MaybeU32 readCached(uint32_t virtAddr, ValueSize valueSize);
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bool writeCached(uint32_t value, uint32_t virtAddr, ValueSize valueSize);
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// Instruction Loop
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int prefetchCount;
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uint32_t prefetch[2];
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MMUFault prefetchFaults[2];
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uint32_t executeInstruction(uint32_t insn);
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uint32_t execDataProcessing(bool I, uint32_t Opcode, bool S, uint32_t Rn, uint32_t Rd, uint32_t Operand2);
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uint32_t execMultiply(uint32_t AS, uint32_t Rd, uint32_t Rn, uint32_t Rs, uint32_t Rm);
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uint32_t execSingleDataSwap(bool B, uint32_t Rn, uint32_t Rd, uint32_t Rm);
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uint32_t execSingleDataTransfer(uint32_t IPUBWL, uint32_t Rn, uint32_t Rd, uint32_t offset);
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uint32_t execBlockDataTransfer(uint32_t PUSWL, uint32_t Rn, uint32_t registerList);
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uint32_t execBranch(bool L, uint32_t offset);
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uint32_t execCP15RegisterTransfer(uint32_t CPOpc, bool L, uint32_t CRn, uint32_t Rd, uint32_t CP, uint32_t CRm);
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};
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