mirror of https://github.com/Treeki/WindEmu.git
220 lines
5.3 KiB
C
220 lines
5.3 KiB
C
/* Copyright (c) 2013-2014 Jeffrey Pfau
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#ifndef ARM_DECODER_H
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#define ARM_DECODER_H
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#include "common.h"
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CXX_GUARD_START
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#include "arm.h"
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// Bit 0: a register is involved with this operand
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// Bit 1: an immediate is invovled with this operand
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// Bit 2: a memory access is invovled with this operand
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// Bit 3: the destination of this operand is affected by this opcode
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// Bit 4: this operand is shifted by a register
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// Bit 5: this operand is shifted by an immediate
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#define ARM_OPERAND_NONE 0x00000000
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#define ARM_OPERAND_REGISTER_1 0x00000001
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#define ARM_OPERAND_IMMEDIATE_1 0x00000002
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#define ARM_OPERAND_MEMORY_1 0x00000004
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#define ARM_OPERAND_AFFECTED_1 0x00000008
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#define ARM_OPERAND_SHIFT_REGISTER_1 0x00000010
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#define ARM_OPERAND_SHIFT_IMMEDIATE_1 0x00000020
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#define ARM_OPERAND_1 0x000000FF
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#define ARM_OPERAND_REGISTER_2 0x00000100
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#define ARM_OPERAND_IMMEDIATE_2 0x00000200
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#define ARM_OPERAND_MEMORY_2 0x00000400
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#define ARM_OPERAND_AFFECTED_2 0x00000800
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#define ARM_OPERAND_SHIFT_REGISTER_2 0x00001000
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#define ARM_OPERAND_SHIFT_IMMEDIATE_2 0x00002000
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#define ARM_OPERAND_2 0x0000FF00
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#define ARM_OPERAND_REGISTER_3 0x00010000
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#define ARM_OPERAND_IMMEDIATE_3 0x00020000
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#define ARM_OPERAND_MEMORY_3 0x00040000
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#define ARM_OPERAND_AFFECTED_3 0x00080000
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#define ARM_OPERAND_SHIFT_REGISTER_3 0x00100000
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#define ARM_OPERAND_SHIFT_IMMEDIATE_3 0x00200000
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#define ARM_OPERAND_3 0x00FF0000
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#define ARM_OPERAND_REGISTER_4 0x01000000
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#define ARM_OPERAND_IMMEDIATE_4 0x02000000
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#define ARM_OPERAND_MEMORY_4 0x04000000
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#define ARM_OPERAND_AFFECTED_4 0x08000000
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#define ARM_OPERAND_SHIFT_REGISTER_4 0x10000000
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#define ARM_OPERAND_SHIFT_IMMEDIATE_4 0x20000000
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#define ARM_OPERAND_4 0xFF000000
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#define ARM_OPERAND_MEMORY (ARM_OPERAND_MEMORY_1 | ARM_OPERAND_MEMORY_2 | ARM_OPERAND_MEMORY_3 | ARM_OPERAND_MEMORY_4)
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#define ARM_MEMORY_REGISTER_BASE 0x0001
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#define ARM_MEMORY_IMMEDIATE_OFFSET 0x0002
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#define ARM_MEMORY_REGISTER_OFFSET 0x0004
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#define ARM_MEMORY_SHIFTED_OFFSET 0x0008
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#define ARM_MEMORY_PRE_INCREMENT 0x0010
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#define ARM_MEMORY_POST_INCREMENT 0x0020
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#define ARM_MEMORY_OFFSET_SUBTRACT 0x0040
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#define ARM_MEMORY_WRITEBACK 0x0080
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#define ARM_MEMORY_DECREMENT_AFTER 0x0000
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#define ARM_MEMORY_INCREMENT_AFTER 0x0100
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#define ARM_MEMORY_DECREMENT_BEFORE 0x0200
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#define ARM_MEMORY_INCREMENT_BEFORE 0x0300
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#define ARM_MEMORY_SPSR_SWAP 0x0400
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#define ARM_PSR_C 1
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#define ARM_PSR_X 2
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#define ARM_PSR_S 4
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#define ARM_PSR_F 8
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#define ARM_PSR_MASK 0xF
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#define MEMORY_FORMAT_TO_DIRECTION(F) (((F) >> 8) & 0x3)
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enum ARMCondition {
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ARM_CONDITION_EQ = 0x0,
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ARM_CONDITION_NE = 0x1,
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ARM_CONDITION_CS = 0x2,
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ARM_CONDITION_CC = 0x3,
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ARM_CONDITION_MI = 0x4,
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ARM_CONDITION_PL = 0x5,
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ARM_CONDITION_VS = 0x6,
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ARM_CONDITION_VC = 0x7,
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ARM_CONDITION_HI = 0x8,
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ARM_CONDITION_LS = 0x9,
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ARM_CONDITION_GE = 0xA,
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ARM_CONDITION_LT = 0xB,
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ARM_CONDITION_GT = 0xC,
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ARM_CONDITION_LE = 0xD,
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ARM_CONDITION_AL = 0xE,
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ARM_CONDITION_NV = 0xF
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};
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enum ARMShifterOperation {
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ARM_SHIFT_NONE = 0,
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ARM_SHIFT_LSL,
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ARM_SHIFT_LSR,
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ARM_SHIFT_ASR,
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ARM_SHIFT_ROR,
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ARM_SHIFT_RRX
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};
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union ARMOperand {
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struct {
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uint8_t reg;
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uint8_t shifterOp;
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union {
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uint8_t shifterReg;
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uint8_t shifterImm;
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uint8_t psrBits;
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};
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};
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int32_t immediate;
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};
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enum ARMMemoryAccessType {
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ARM_ACCESS_WORD = 4,
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ARM_ACCESS_HALFWORD = 2,
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ARM_ACCESS_SIGNED_HALFWORD = 10,
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ARM_ACCESS_BYTE = 1,
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ARM_ACCESS_SIGNED_BYTE = 9,
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ARM_ACCESS_TRANSLATED_WORD = 20,
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ARM_ACCESS_TRANSLATED_BYTE = 17
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};
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enum ARMBranchType {
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ARM_BRANCH_NONE = 0,
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ARM_BRANCH = 1,
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ARM_BRANCH_INDIRECT = 2,
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ARM_BRANCH_LINKED = 4
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};
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struct ARMMemoryAccess {
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uint8_t baseReg;
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uint8_t width;
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uint16_t format;
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union ARMOperand offset;
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};
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enum ARMMnemonic {
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ARM_MN_ILL = 0,
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ARM_MN_ADC,
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ARM_MN_ADD,
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ARM_MN_AND,
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ARM_MN_ASR,
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ARM_MN_B,
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ARM_MN_BIC,
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ARM_MN_BKPT,
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ARM_MN_BL,
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ARM_MN_BX,
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ARM_MN_CMN,
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ARM_MN_CMP,
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ARM_MN_EOR,
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ARM_MN_LDM,
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ARM_MN_LDR,
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ARM_MN_LSL,
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ARM_MN_LSR,
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ARM_MN_MLA,
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ARM_MN_MOV,
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ARM_MN_MRS,
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ARM_MN_MSR,
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ARM_MN_MUL,
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ARM_MN_MVN,
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ARM_MN_NEG,
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ARM_MN_ORR,
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ARM_MN_ROR,
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ARM_MN_RSB,
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ARM_MN_RSC,
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ARM_MN_SBC,
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ARM_MN_SMLAL,
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ARM_MN_SMULL,
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ARM_MN_STM,
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ARM_MN_STR,
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ARM_MN_SUB,
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ARM_MN_SWI,
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ARM_MN_SWP,
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ARM_MN_TEQ,
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ARM_MN_TST,
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ARM_MN_UMLAL,
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ARM_MN_UMULL,
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ARM_MN_MAX
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};
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enum {
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ARM_CPSR = 16,
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ARM_SPSR = 17
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};
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struct ARMInstructionInfo {
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uint32_t opcode;
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union ARMOperand op1;
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union ARMOperand op2;
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union ARMOperand op3;
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union ARMOperand op4;
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struct ARMMemoryAccess memory;
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int operandFormat;
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bool traps : 1;
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bool affectsCPSR : 1;
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unsigned branchType : 3;
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unsigned condition : 4;
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unsigned mnemonic : 6;
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unsigned iCycles : 3;
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unsigned cCycles : 4;
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unsigned sInstructionCycles : 4;
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unsigned nInstructionCycles : 4;
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unsigned sDataCycles : 10;
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unsigned nDataCycles : 10;
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};
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void ARMDecodeARM(uint32_t opcode, struct ARMInstructionInfo* info);
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int ARMDisassemble(struct ARMInstructionInfo* info, uint32_t pc, char* buffer, int blen);
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CXX_GUARD_END
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#endif
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