461 lines
15 KiB
Plaintext
461 lines
15 KiB
Plaintext
/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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* Automatically generated file. DO NOT EDIT.
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* Espressif IoT Development Framework (ESP-IDF) 5.4.0 Configuration Header
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*/
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/* List of deprecated options */
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/* CPU instruction prefetch padding size for flash mmap scenario */
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/*
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* PMP region granularity size
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* Software may determine the PMP granularity by writing zero to pmp0cfg, then writing all ones
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* to pmpaddr0, then reading back pmpaddr0. If G is the index of the least-significant bit set,
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* the PMP granularity is 2^G+2 bytes.
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*/
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/* CPU instruction prefetch padding size for memory protection scenario */
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/* Memory alignment size for PMS */
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/* rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files). For rtc_timer_data_in_rtc_mem section. */
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/* Default entry point */
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ENTRY(call_start_cpu0);
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SECTIONS
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{
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/**
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* RTC fast memory holds RTC wake stub code,
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* including from any source file named rtc_wake_stub*.c
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*/
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.rtc.text :
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{
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/* Align the start of RTC code region as per PMP granularity
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* this ensures we do not overwrite the permissions for the previous
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* region (ULP mem) regardless of its end alignment
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*/
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. = ALIGN(4);
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_rtc_fast_start = ABSOLUTE(.);
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. = ALIGN(4);
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_rtc_text_start = ABSOLUTE(.);
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*(.rtc.entry.text)
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mapping[rtc_text]
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*rtc_wake_stub*.*(.text .text.*)
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*(.rtc_text_end_test)
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/* Align the end of RTC code region as per PMP granularity */
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. = ALIGN(4);
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_rtc_text_end = ABSOLUTE(.);
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} > lp_ram_seg
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/**
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* This section located in RTC FAST Memory area.
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* It holds data marked with RTC_FAST_ATTR attribute.
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* See the file "esp_attr.h" for more information.
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*/
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.rtc.force_fast :
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{
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. = ALIGN(4);
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_rtc_force_fast_start = ABSOLUTE(.);
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mapping[rtc_force_fast]
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*(.rtc.force_fast .rtc.force_fast.*)
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. = ALIGN(4);
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_rtc_force_fast_end = ABSOLUTE(.);
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} > lp_ram_seg
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/**
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* RTC data section holds RTC wake stub
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* data/rodata, including from any source file
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* named rtc_wake_stub*.c and the data marked with
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* RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
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*/
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.rtc.data :
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{
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_rtc_data_start = ABSOLUTE(.);
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mapping[rtc_data]
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*rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .srodata.*)
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_rtc_data_end = ABSOLUTE(.);
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} > lp_ram_seg
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/* RTC bss, from any source file named rtc_wake_stub*.c */
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.rtc.bss (NOLOAD) :
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{
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_rtc_bss_start = ABSOLUTE(.);
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*rtc_wake_stub*.*(.bss .bss.* .sbss .sbss.*)
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*rtc_wake_stub*.*(COMMON)
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mapping[rtc_bss]
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_rtc_bss_end = ABSOLUTE(.);
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} > lp_ram_seg
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/**
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* This section holds data that should not be initialized at power up
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* and will be retained during deep sleep.
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* User data marked with RTC_NOINIT_ATTR will be placed
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* into this section. See the file "esp_attr.h" for more information.
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*/
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.rtc_noinit (NOLOAD):
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{
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. = ALIGN(4);
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_rtc_noinit_start = ABSOLUTE(.);
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*(.rtc_noinit .rtc_noinit.*)
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. = ALIGN(4);
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_rtc_noinit_end = ABSOLUTE(.);
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} > lp_ram_seg
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/**
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* This section located in RTC SLOW Memory area.
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* It holds data marked with RTC_SLOW_ATTR attribute.
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* See the file "esp_attr.h" for more information.
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*/
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.rtc.force_slow :
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{
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. = ALIGN(4);
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_rtc_force_slow_start = ABSOLUTE(.);
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*(.rtc.force_slow .rtc.force_slow.*)
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. = ALIGN(4);
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_rtc_force_slow_end = ABSOLUTE(.);
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} > lp_ram_seg
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/**
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* This section holds RTC data that should have fixed addresses.
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* The data are not initialized at power-up and are retained during deep
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* sleep.
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*/
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.rtc_reserved (NOLOAD):
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{
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. = ALIGN(4);
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_rtc_reserved_start = ABSOLUTE(.);
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/**
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* New data can only be added here to ensure existing data are not moved.
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* Because data have adhered to the end of the segment and code is relied
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* on it.
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* >> put new data here <<
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*/
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*(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*)
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KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*))
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_rtc_reserved_end = ABSOLUTE(.);
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} > rtc_reserved_seg
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_rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start;
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ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)),
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"RTC reserved segment data does not fit.")
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/* Get size of rtc slow data based on rtc_data_location alias */
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_rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
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? (_rtc_force_slow_end - _rtc_data_start)
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: (_rtc_force_slow_end - _rtc_force_slow_start);
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_rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
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? (_rtc_force_fast_end - _rtc_fast_start)
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: (_rtc_noinit_end - _rtc_fast_start);
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ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)),
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"RTC_SLOW segment data does not fit.")
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ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)),
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"RTC_FAST segment data does not fit.")
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.iram0.text :
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{
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_iram_start = ABSOLUTE(.);
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/* Vectors go to start of IRAM */
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ASSERT(ABSOLUTE(.) % 0x100 == 0, "vector address must be 256 byte aligned");
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KEEP(*(.exception_vectors_table.text));
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KEEP(*(.exception_vectors.text));
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. = ALIGN(4);
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_invalid_pc_placeholder = ABSOLUTE(.);
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/* Code marked as running out of IRAM */
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_iram_text_start = ABSOLUTE(.);
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mapping[iram0_text]
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} > sram_seg
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/* Marks the end of IRAM code segment */
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.iram0.text_end (NOLOAD) :
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{
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/* Align the end of code region as per PMP region granularity */
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. = ALIGN(4);
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. = ALIGN(4);
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_iram_text_end = ABSOLUTE(.);
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} > sram_seg
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.iram0.data :
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{
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. = ALIGN(16);
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_iram_data_start = ABSOLUTE(.);
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mapping[iram0_data]
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_iram_data_end = ABSOLUTE(.);
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} > sram_seg
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.iram0.bss (NOLOAD) :
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{
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. = ALIGN(16);
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_iram_bss_start = ABSOLUTE(.);
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mapping[iram0_bss]
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_iram_bss_end = ABSOLUTE(.);
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. = ALIGN(16);
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_iram_end = ABSOLUTE(.);
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} > sram_seg
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.dram0.data :
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{
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_data_start = ABSOLUTE(.);
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*(.gnu.linkonce.d.*)
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*(.data1)
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__global_pointer$ = . + 0x800;
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*(.sdata)
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*(.sdata.*)
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*(.gnu.linkonce.s.*)
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*(.gnu.linkonce.s2.*)
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*(.jcr)
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mapping[dram0_data]
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_data_end = ABSOLUTE(.);
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} > sram_seg
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/**
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* This section holds data that should not be initialized at power up.
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* The section located in Internal SRAM memory region. The macro _NOINIT
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* can be used as attribute to place data into this section.
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* See the "esp_attr.h" file for more information.
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*/
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.noinit (NOLOAD):
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{
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. = ALIGN(4);
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_noinit_start = ABSOLUTE(.);
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*(.noinit .noinit.*)
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. = ALIGN(4);
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_noinit_end = ABSOLUTE(.);
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} > sram_seg
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/* Shared RAM */
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.dram0.bss (NOLOAD) :
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{
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. = ALIGN(8);
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_bss_start = ABSOLUTE(.);
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/**
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* ldgen places all bss-related data to mapping[dram0_bss]
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* (See components/esp_system/app.lf).
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*/
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mapping[dram0_bss]
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. = ALIGN(8);
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_bss_end = ABSOLUTE(.);
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} > sram_seg
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.flash.text :
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{
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_stext = .;
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/**
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* Mark the start of flash.text.
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* This can be used by the MMU driver to maintain the virtual address.
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*/
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_instruction_reserved_start = ABSOLUTE(.);
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_text_start = ABSOLUTE(.);
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mapping[flash_text]
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*(.stub)
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*(.gnu.linkonce.t.*)
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*(.gnu.warning)
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*(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
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/**
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* CPU will try to prefetch up to 16 bytes of of instructions.
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* This means that any configuration (e.g. MMU, PMS) must allow
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* safe access to up to 16 bytes after the last real instruction, add
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* dummy bytes to ensure this
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*/
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. += 16;
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_text_end = ABSOLUTE(.);
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/**
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* Mark the flash.text end.
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* This can be used for MMU driver to maintain virtual address.
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*/
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_instruction_reserved_end = ABSOLUTE(.);
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_etext = .;
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/**
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* Similar to _iram_start, this symbol goes here so it is
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* resolved by addr2line in preference to the first symbol in
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* the flash.text segment.
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*/
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_flash_cache_start = ABSOLUTE(0);
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} > default_code_seg
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/**
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* Dummy section represents the .flash.text section but in default_rodata_seg.
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* Thus, it must have its alignment and (at least) its size.
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*/
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.flash_rodata_dummy (NOLOAD):
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{
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_flash_rodata_dummy_start = .;
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. = ALIGN(ALIGNOF(.flash.text)) + SIZEOF(.flash.text);
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/* Add alignment of MMU page size + 0x20 bytes for the mapping header. */
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. = ALIGN(0x10000) + 0x20;
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} > default_rodata_seg
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.flash.appdesc : ALIGN(0x10)
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{
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/**
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* Mark flash.rodata start.
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* This can be used for mmu driver to maintain virtual address
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*/
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_rodata_reserved_start = ABSOLUTE(.);
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_rodata_start = ABSOLUTE(.);
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/* !DO NOT PUT ANYTHING BEFORE THIS! */
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/* Should be the first. App version info. */
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*(.rodata_desc .rodata_desc.*)
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/* Should be the second. Custom app version info. */
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*(.rodata_custom_desc .rodata_custom_desc.*)
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/**
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* Create an empty gap within this section. Thanks to this, the end of this
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* section will match .flash.rodata's begin address. Thus, both sections
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* will be merged when creating the final bin image.
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*/
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. = ALIGN(ALIGNOF(.flash.rodata));
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} > default_rodata_seg
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ASSERT((ADDR(.flash.rodata) == ADDR(.flash.appdesc) + SIZEOF(.flash.appdesc)), "The gap between .flash.appdesc and .flash.rodata must not exist to produce the final bin image.")
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.flash.rodata : ALIGN(0x10)
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{
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_flash_rodata_start = ABSOLUTE(.);
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mapping[flash_rodata]
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*(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
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*(.gnu.linkonce.r.*)
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*(.rodata1)
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*(.gcc_except_table .gcc_except_table.*)
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*(.gnu.linkonce.e.*)
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/**
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* C++ constructor tables.
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*
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* Excluding crtbegin.o/crtend.o since IDF doesn't use the toolchain crt.
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*
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* RISC-V gcc is configured with --enable-initfini-array so it emits
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* .init_array section instead. But the init_priority sections will be
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* sorted for iteration in ascending order during startup.
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* The rest of the init_array sections is sorted for iteration in descending
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* order during startup, however. Hence a different section is generated for
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* the init_priority functions which is iterated in ascending order during
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* startup. The corresponding code can be found in startup.c.
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*/
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. = ALIGN(4);
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__init_priority_array_start = ABSOLUTE(.);
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KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))
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__init_priority_array_end = ABSOLUTE(.);
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. = ALIGN(4);
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__init_array_start = ABSOLUTE(.);
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KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))
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__init_array_end = ABSOLUTE(.);
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/* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */
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. = ALIGN(4);
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soc_reserved_memory_region_start = ABSOLUTE(.);
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KEEP (*(.reserved_memory_address))
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soc_reserved_memory_region_end = ABSOLUTE(.);
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/* System init functions registered via ESP_SYSTEM_INIT_FN */
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. = ALIGN(4);
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_esp_system_init_fn_array_start = ABSOLUTE(.);
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KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*)))
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_esp_system_init_fn_array_end = ABSOLUTE(.);
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_rodata_end = ABSOLUTE(.);
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. = ALIGN(ALIGNOF(.eh_frame_hdr));
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} > default_rodata_seg
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ASSERT((ADDR(.eh_frame_hdr) == ADDR(.flash.rodata) + SIZEOF(.flash.rodata)), "The gap between .flash.rodata and .eh_frame_hdr must not exist to produce the final bin image.")
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.eh_frame_hdr :
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{
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. = ALIGN(ALIGNOF(.eh_frame));
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} > default_rodata_seg
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ASSERT((ADDR(.eh_frame) == ADDR(.eh_frame_hdr) + SIZEOF(.eh_frame_hdr)), "The gap between .eh_frame_hdr and .eh_frame must not exist to produce the final bin image.")
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.eh_frame :
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{
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. = ALIGN(ALIGNOF(.flash.tdata));
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} > default_rodata_seg
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ASSERT((ADDR(.flash.tdata) == ADDR(.eh_frame) + SIZEOF(.eh_frame)), "The gap between .eh_frame and .flash.tdata must not exist to produce the final bin image.")
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.flash.tdata :
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{
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_thread_local_data_start = ABSOLUTE(.);
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*(.tdata .tdata.* .gnu.linkonce.td.*)
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. = ALIGN(ALIGNOF(.flash.tbss));
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_thread_local_data_end = ABSOLUTE(.);
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} > default_rodata_seg
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ASSERT((ADDR(.flash.tbss) == ADDR(.flash.tdata) + SIZEOF(.flash.tdata)), "The gap between .flash.tdata and .flash.tbss must not exist to produce the final bin image.")
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.flash.tbss (NOLOAD) :
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{
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_thread_local_bss_start = ABSOLUTE(.);
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|
*(.tbss .tbss.* .gnu.linkonce.tb.*)
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|
*(.tcommon .tcommon.*)
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_thread_local_bss_end = ABSOLUTE(.);
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} > default_rodata_seg
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/**
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* This section contains all the rodata that is not used
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* at runtime, helping to avoid an increase in binary size.
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*/
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.flash.rodata_noload (NOLOAD) :
|
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{
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|
/**
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|
* This symbol marks the end of flash.rodata. It can be utilized by the MMU
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|
* driver to maintain the virtual address.
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|
* NOLOAD rodata may not be included in this section.
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|
*/
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_rodata_reserved_end = ADDR(.flash.tbss);
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mapping[rodata_noload]
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} > default_rodata_seg
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|
/* Marks the end of data, bss and possibly rodata */
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|
.dram0.heap_start (NOLOAD) :
|
|
{
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|
|
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. = ALIGN(16);
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_heap_start = ABSOLUTE(.);
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} > sram_seg
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|
/* DWARF 1 */
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|
.debug 0 : { *(.debug) }
|
|
.line 0 : { *(.line) }
|
|
/* GNU DWARF 1 extensions */
|
|
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
|
.debug_sfnames 0 : { *(.debug_sfnames) }
|
|
/* DWARF 1.1 and DWARF 2 */
|
|
.debug_aranges 0 : { *(.debug_aranges) }
|
|
.debug_pubnames 0 : { *(.debug_pubnames) }
|
|
/* DWARF 2 */
|
|
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
|
.debug_abbrev 0 : { *(.debug_abbrev) }
|
|
.debug_line 0 : { *(.debug_line) }
|
|
.debug_frame 0 : { *(.debug_frame) }
|
|
.debug_str 0 : { *(.debug_str) }
|
|
.debug_loc 0 : { *(.debug_loc) }
|
|
.debug_macinfo 0 : { *(.debug_macinfo) }
|
|
.debug_pubtypes 0 : { *(.debug_pubtypes) }
|
|
/* DWARF 3 */
|
|
.debug_ranges 0 : { *(.debug_ranges) }
|
|
/* SGI/MIPS DWARF 2 extensions */
|
|
.debug_weaknames 0 : { *(.debug_weaknames) }
|
|
.debug_funcnames 0 : { *(.debug_funcnames) }
|
|
.debug_typenames 0 : { *(.debug_typenames) }
|
|
.debug_varnames 0 : { *(.debug_varnames) }
|
|
/* GNU DWARF 2 extensions */
|
|
.debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
|
|
.debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
|
|
/* DWARF 4 */
|
|
.debug_types 0 : { *(.debug_types) }
|
|
/* DWARF 5 */
|
|
.debug_addr 0 : { *(.debug_addr) }
|
|
.debug_line_str 0 : { *(.debug_line_str) }
|
|
.debug_loclists 0 : { *(.debug_loclists) }
|
|
.debug_macro 0 : { *(.debug_macro) }
|
|
.debug_names 0 : { *(.debug_names) }
|
|
.debug_rnglists 0 : { *(.debug_rnglists) }
|
|
.debug_str_offsets 0 : { *(.debug_str_offsets) }
|
|
.comment 0 : { *(.comment) }
|
|
.note.GNU-stack 0: { *(.note.GNU-stack) }
|
|
.riscv.attributes 0: { *(.riscv.attributes) }
|
|
/DISCARD/ :
|
|
{
|
|
/**
|
|
* Discarding .rela.* sections results in the following mapping:
|
|
* .rela.text.* -> .text.*
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|
* .rela.data.* -> .data.*
|
|
* And so forth...
|
|
*/
|
|
*(.rela.*)
|
|
*(.got .got.plt) /* TODO: GCC-382 */
|
|
*(.eh_frame_hdr)
|
|
*(.eh_frame)
|
|
}
|
|
}
|