Test:adds support for breaking crc

This commit is contained in:
Simon Albinsson
2018-04-12 21:22:14 +00:00
parent a38a71d186
commit 5c6086d0e2

View File

@@ -10,16 +10,17 @@ answers = {
(0x20, 0x15): add_crc([0,0]) ,#GET_FEATURES
(0x20, 0x03): None ,#IAQ_INIT
(0x20, 0x08): [1, 144, 76, 0, 6, 39] ,#IAQ_MEASURE
(0x20, 0x32): add_crc([0xD4,0x00]),#IAQ_SELFTEST
(0x20, 0x15): add_crc([0x00,0x00])*2 ,#GET_BASELINE Invalid, should be more realistic data..
(0x20, 0x32): add_crc([0xD4,0x00]) ,#IAQ_SELFTEST
(0x20, 0x15): [133, 152, 85, 138, 32, 202] ,#GET_BASELINE
(0x20, 0x1e): None,#SET_BASELINE
}
class MockSMBus:
def __init__(s):
def __init__(s,break_crc=False):
s.status=None
s.last=None
s.addr=None
s._break_crc=break_crc
def i2c_rdwr(s,*msgs):
for m in msgs:
@@ -38,6 +39,10 @@ class MockSMBus:
raise AssertionError("tired to read before write")
for i in range(len(s.status)):
msg.buf[i]=chr(s.status[i])
if s._break_crc and i%3 == 2:
msg.buf[i]=msg.buf[i]^42
def _process_write(s,msg):
s.status = answers[tuple(msg)]
s.last=msg