Test:adds support for breaking crc
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@@ -10,16 +10,17 @@ answers = {
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(0x20, 0x15): add_crc([0,0]) ,#GET_FEATURES
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(0x20, 0x03): None ,#IAQ_INIT
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(0x20, 0x08): [1, 144, 76, 0, 6, 39] ,#IAQ_MEASURE
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(0x20, 0x32): add_crc([0xD4,0x00]),#IAQ_SELFTEST
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(0x20, 0x15): add_crc([0x00,0x00])*2 ,#GET_BASELINE Invalid, should be more realistic data..
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(0x20, 0x32): add_crc([0xD4,0x00]) ,#IAQ_SELFTEST
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(0x20, 0x15): [133, 152, 85, 138, 32, 202] ,#GET_BASELINE
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(0x20, 0x1e): None,#SET_BASELINE
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}
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class MockSMBus:
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def __init__(s):
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def __init__(s,break_crc=False):
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s.status=None
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s.last=None
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s.addr=None
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s._break_crc=break_crc
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def i2c_rdwr(s,*msgs):
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for m in msgs:
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@@ -38,6 +39,10 @@ class MockSMBus:
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raise AssertionError("tired to read before write")
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for i in range(len(s.status)):
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msg.buf[i]=chr(s.status[i])
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if s._break_crc and i%3 == 2:
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msg.buf[i]=msg.buf[i]^42
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def _process_write(s,msg):
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s.status = answers[tuple(msg)]
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s.last=msg
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