Merge tag 'xilinx-for-v2022.07-rc1-v2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.07-rc1 v2

xilinx:
- Allow booting bigger kernels till 100MB

zynqmp:
- DT updates (reset IDs)
- Remove unneeded low level uart initialization from psu_init*
- Enable PWM features
- Add support for 1EG device

serial_zynq:
- Change fifo behavior in DEBUG mode

zynq_sdhci:
- Fix BASECLK setting calculation

clk_zynqmp:
- Add support for showing video clock

gpio:
- Update slg driver to handle DT flags

net:
- Update ethernet_id code to support also DM_ETH_PHY
- Add support for DM_ETH_PHY in gem driver
- Enable dynamic mode for SGMII config in gem driver

pwm:
- Add driver for cadence PWM

versal:
- Add support for reserved memory

firmware:
- Handle PD enabling for SPL
- Add support for IOUSLCR SGMII configurations

include:
- Sync phy.h with Linux
- Update xilinx power domain dt binding headers

drivers/net/phy/ethernet_id.c

@@ -12,7 +12,7 @@
 #include <asm/gpio.h>
 
 struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev,
-				      phy_interface_t interface)
+				      int phyaddr, phy_interface_t interface)
 {
 	struct phy_device *phydev;
 	struct ofnode_phandle_args phandle_args;
@@ -33,35 +33,42 @@ struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev,
 
 	ret = ofnode_read_eth_phy_id(node, &vendor, &device);
 	if (ret) {
-		dev_err(dev, "Failed to read eth PHY id, err: %d\n", ret);
+		debug("Failed to read eth PHY id, err: %d\n", ret);
 		return NULL;
 	}
 
-	ret = gpio_request_by_name_nodev(node, "reset-gpios", 0, &gpio,
-					 GPIOD_ACTIVE_LOW);
-	if (!ret) {
-		assert = ofnode_read_u32_default(node, "reset-assert-us", 0);
-		deassert = ofnode_read_u32_default(node,
-						   "reset-deassert-us", 0);
-		ret = dm_gpio_set_value(&gpio, 1);
-		if (ret) {
-			dev_err(dev, "Failed assert gpio, err: %d\n", ret);
-			return NULL;
+	if (!IS_ENABLED(CONFIG_DM_ETH_PHY)) {
+		ret = gpio_request_by_name_nodev(node, "reset-gpios", 0, &gpio,
+						 GPIOD_ACTIVE_LOW);
+		if (!ret) {
+			assert = ofnode_read_u32_default(node,
+							 "reset-assert-us", 0);
+			deassert = ofnode_read_u32_default(node,
+							   "reset-deassert-us",
+							   0);
+			ret = dm_gpio_set_value(&gpio, 1);
+			if (ret) {
+				dev_err(dev,
+					"Failed assert gpio, err: %d\n", ret);
+				return NULL;
+			}
+
+			udelay(assert);
+
+			ret = dm_gpio_set_value(&gpio, 0);
+			if (ret) {
+				dev_err(dev,
+					"Failed deassert gpio, err: %d\n",
+					ret);
+				return NULL;
+			}
+
+			udelay(deassert);
 		}
-
-		udelay(assert);
-
-		ret = dm_gpio_set_value(&gpio, 0);
-		if (ret) {
-			dev_err(dev, "Failed deassert gpio, err: %d\n", ret);
-			return NULL;
-		}
-
-		udelay(deassert);
 	}
 
 	id =  vendor << 16 | device;
-	phydev = phy_device_create(bus, 0, id, false, interface);
+	phydev = phy_device_create(bus, phyaddr, id, false, interface);
 	if (phydev)
 		phydev->node = node;
 

drivers/net/phy/phy.c

@@ -1049,7 +1049,7 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr,
 
 #ifdef CONFIG_PHY_ETHERNET_ID
 	if (!phydev)
-		phydev = phy_connect_phy_id(bus, dev, interface);
+		phydev = phy_connect_phy_id(bus, dev, addr, interface);
 #endif
 
 #ifdef CONFIG_PHY_XILINX_GMII2RGMII