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rockchip: Ensure memory size is available in RK3399 SPL

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At present gd->ram_size is 0 in SPL, meaning that it is not possible to
enable the cache. Correct this by always populating the RAM size
correctly.

This increases code size by about 500 bytes in SPL, since it must call
the rather large rockchip_sdram_size() function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
This commit is contained in:
Simon Glass
2024-08-01 06:47:22 -06:00
committed by Tom Rini
parent cafde93ec0
commit 0450e91c38
1 changed files with 14 additions and 8 deletions
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22
drivers/ram/rockchip/sdram_rk3399.c
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@@ -3142,19 +3142,25 @@ static int rk3399_dmc_init(struct udevice *dev)
static int rk3399_dmc_probe(struct udevice *dev)
{
struct dram_info *priv = dev_get_priv(dev);
#if defined(CONFIG_TPL_BUILD) || \
(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
if (rk3399_dmc_init(dev))
return 0;
#else
struct dram_info *priv = dev_get_priv(dev);
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size =
rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
#endif
/*
* There is no point in checking the SDRAM size in TPL as it is not
* used, so avoid the code size increment.
*/
if (!IS_ENABLED(CONFIG_TPL_BUILD)) {
priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
priv->info.base = CFG_SYS_SDRAM_BASE;
priv->info.size = rockchip_sdram_size(
(phys_addr_t)&priv->pmugrf->os_reg2);
}
return 0;
}