x86: apl: Add pinctrl driver
Add a driver for the Apollo Lake pinctrl. This mostly makes use of the common Intel pinctrl support. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
Bin Meng
@@ -5,12 +5,22 @@
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if PINCTRL_INTEL
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config INTEL_PINCTRL_DUAL_ROUTE_SUPPORT
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def_bool y
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bool
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default y
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config INTEL_PINCTRL_PADCFG_PADTOL
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def_bool n
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bool n
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config INTEL_PINCTRL_IOSTANDBY
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def_bool y
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bool
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default y
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config PINCTRL_INTEL_APL
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bool "Support Intel Apollo Lake (APL)"
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help
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Add support for Intel Apollo Lake pin-control and pin-mux settings.
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These are mostly read from the device tree, with the early-pads
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property in the host bridge and the pads property in the fsp-s
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subnode of the host bridge.
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endif
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@@ -3,3 +3,4 @@
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# Copyright 2019 Google LLC
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obj-y += pinctrl.o
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obj-$(CONFIG_PINCTRL_INTEL_APL) += pinctrl_apl.o
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192
drivers/pinctrl/intel/pinctrl_apl.c
Normal file
192
drivers/pinctrl/intel/pinctrl_apl.c
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@@ -0,0 +1,192 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017 Intel Corp.
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* Copyright 2019 Google LLC
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*
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* Taken partly from coreboot gpio.c
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*/
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#define LOG_CATEGORY UCLASS_GPIO
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#include <common.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <p2sb.h>
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#include <asm/intel_pinctrl.h>
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#include <asm-generic/gpio.h>
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#include <asm/intel_pinctrl_defs.h>
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/**
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* struct apl_gpio_platdata - platform data for each device
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*
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* @dtplat: of-platdata data from C struct
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*/
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struct apl_gpio_platdata {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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/* Put this first since driver model will copy the data here */
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struct dtd_intel_apl_pinctrl dtplat;
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#endif
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};
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static const struct reset_mapping rst_map[] = {
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{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
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{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
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};
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/* Groups for each community */
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static const struct pad_group apl_community_n_groups[] = {
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INTEL_GPP(N_OFFSET, N_OFFSET, GPIO_31), /* NORTH 0 */
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INTEL_GPP(N_OFFSET, GPIO_32, JTAG_TRST_B), /* NORTH 1 */
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INTEL_GPP(N_OFFSET, JTAG_TMS, SVID0_CLK), /* NORTH 2 */
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};
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static const struct pad_group apl_community_w_groups[] = {
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INTEL_GPP(W_OFFSET, W_OFFSET, OSC_CLK_OUT_1), /* WEST 0 */
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INTEL_GPP(W_OFFSET, OSC_CLK_OUT_2, SUSPWRDNACK),/* WEST 1 */
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};
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static const struct pad_group apl_community_sw_groups[] = {
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INTEL_GPP(SW_OFFSET, SW_OFFSET, SMB_ALERTB), /* SOUTHWEST 0 */
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INTEL_GPP(SW_OFFSET, SMB_CLK, LPC_FRAMEB), /* SOUTHWEST 1 */
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};
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static const struct pad_group apl_community_nw_groups[] = {
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INTEL_GPP(NW_OFFSET, NW_OFFSET, PROCHOT_B), /* NORTHWEST 0 */
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INTEL_GPP(NW_OFFSET, PMIC_I2C_SCL, GPIO_106), /* NORTHWEST 1 */
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INTEL_GPP(NW_OFFSET, GPIO_109, GPIO_123), /* NORTHWEST 2 */
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};
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/* TODO(sjg@chromium.org): Consider moving this to device tree */
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static const struct pad_community apl_gpio_communities[] = {
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{
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.port = PID_GPIO_N,
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.first_pad = N_OFFSET,
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.last_pad = SVID0_CLK,
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.num_gpi_regs = NUM_N_GPI_REGS,
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.gpi_status_offset = NUM_NW_GPI_REGS + NUM_W_GPI_REGS
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+ NUM_SW_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_int_sts_reg_0 = GPI_INT_STS_0,
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.gpi_int_en_reg_0 = GPI_INT_EN_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPIO_GPE_N",
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.acpi_path = "\\_SB.GPO0",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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.groups = apl_community_n_groups,
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.num_groups = ARRAY_SIZE(apl_community_n_groups),
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}, {
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.port = PID_GPIO_NW,
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.first_pad = NW_OFFSET,
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.last_pad = GPIO_123,
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.num_gpi_regs = NUM_NW_GPI_REGS,
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.gpi_status_offset = NUM_W_GPI_REGS + NUM_SW_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_int_sts_reg_0 = GPI_INT_STS_0,
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.gpi_int_en_reg_0 = GPI_INT_EN_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPIO_GPE_NW",
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.acpi_path = "\\_SB.GPO1",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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.groups = apl_community_nw_groups,
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.num_groups = ARRAY_SIZE(apl_community_nw_groups),
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}, {
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.port = PID_GPIO_W,
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.first_pad = W_OFFSET,
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.last_pad = SUSPWRDNACK,
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.num_gpi_regs = NUM_W_GPI_REGS,
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.gpi_status_offset = NUM_SW_GPI_REGS,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_int_sts_reg_0 = GPI_INT_STS_0,
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.gpi_int_en_reg_0 = GPI_INT_EN_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPIO_GPE_W",
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.acpi_path = "\\_SB.GPO2",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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.groups = apl_community_w_groups,
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.num_groups = ARRAY_SIZE(apl_community_w_groups),
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}, {
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.port = PID_GPIO_SW,
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.first_pad = SW_OFFSET,
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.last_pad = LPC_FRAMEB,
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.num_gpi_regs = NUM_SW_GPI_REGS,
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.gpi_status_offset = 0,
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.pad_cfg_base = PAD_CFG_BASE,
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.host_own_reg_0 = HOSTSW_OWN_REG_0,
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.gpi_int_sts_reg_0 = GPI_INT_STS_0,
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.gpi_int_en_reg_0 = GPI_INT_EN_0,
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.gpi_smi_sts_reg_0 = GPI_SMI_STS_0,
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.gpi_smi_en_reg_0 = GPI_SMI_EN_0,
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.max_pads_per_group = GPIO_MAX_NUM_PER_GROUP,
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.name = "GPIO_GPE_SW",
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.acpi_path = "\\_SB.GPO3",
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.reset_map = rst_map,
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.num_reset_vals = ARRAY_SIZE(rst_map),
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.groups = apl_community_sw_groups,
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.num_groups = ARRAY_SIZE(apl_community_sw_groups),
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},
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};
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static int apl_pinctrl_ofdata_to_platdata(struct udevice *dev)
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{
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struct p2sb_child_platdata *pplat;
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const struct pad_community *comm = NULL;
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int i;
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct apl_gpio_platdata *plat = dev_get_platdata(dev);
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int ret;
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/*
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* It would be nice to do this in the bind() method, but with
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* of-platdata binding happens in the order that DM finds things in the
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* linker list (i.e. alphabetical order by driver name). So the GPIO
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* device may well be bound before its parent (p2sb), and this call
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* will fail if p2sb is not bound yet.
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*
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* TODO(sjg@chromium.org): Add a parent pointer to child devices in dtoc
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*/
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ret = p2sb_set_port_id(dev, plat->dtplat.intel_p2sb_port_id);
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if (ret)
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return log_msg_ret("Could not set port id", ret);
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#endif
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/* Attach this device to its community structure */
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pplat = dev_get_parent_platdata(dev);
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for (i = 0; i < ARRAY_SIZE(apl_gpio_communities); i++) {
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if (apl_gpio_communities[i].port == pplat->pid)
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comm = &apl_gpio_communities[i];
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}
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return intel_pinctrl_ofdata_to_platdata(dev, comm, 2);
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}
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static const struct udevice_id apl_gpio_ids[] = {
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{ .compatible = "intel,apl-pinctrl"},
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{ }
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};
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U_BOOT_DRIVER(apl_pinctrl_drv) = {
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.name = "intel_apl_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = apl_gpio_ids,
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.probe = intel_pinctrl_probe,
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.ops = &intel_pinctrl_ops,
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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.bind = dm_scan_fdt_dev,
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#endif
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.ofdata_to_platdata = apl_pinctrl_ofdata_to_platdata,
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.priv_auto_alloc_size = sizeof(struct intel_pinctrl_priv),
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.platdata_auto_alloc_size = sizeof(struct apl_gpio_platdata),
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};
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