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drivers/arm: Implement acpi_fill_madt

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Fill the MADT table in the GIC driver and armv8 CPU driver to
drop SoC specific code. While the GIC only needs devicetree
data, the CPU driver needs additional information stored in
the cpu_plat struct.

While on it update the only board making use of the existing
drivers and writing ACPI MADT in mainboard code.

TEST: Booted on QEMU sbsa-ref using GICV3 driver model generated MADT.
      Booted on QEMU raspb4 using GICV2 driver model generated MADT.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Simon Glass <sjg@chromium.org>
This commit is contained in:
Patrick Rudolph
2024-10-23 15:20:06 +02:00
committed by Tom Rini
parent f116feadea
commit 142f92bf04
4 changed files with 178 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/cpu/Kconfig
View File

@@ -29,6 +29,7 @@ config CPU_RISCV
config CPU_ARMV8
bool "Enable generic ARMv8 CPU driver"
depends on CPU && ARM64
select IRQ
help
Support CPU cores for armv8 architecture.

80
drivers/cpu/armv8_cpu.c
View File

@@ -4,10 +4,11 @@
*/
#include <cpu.h>
#include <dm.h>
#include <irq.h>
#include <acpi/acpigen.h>
#include <asm/armv8/cpu.h>
#include <dm/acpi.h>
#include <asm/io.h>
#include <dm/acpi.h>
#include <linux/bitops.h>
#include <linux/printk.h>
#include <linux/sizes.h>
@@ -47,8 +48,85 @@ int armv8_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
return 0;
}
int armv8_cpu_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx)
{
struct acpi_madt_gicc *gicc;
struct cpu_plat *cpu_plat;
struct udevice *gic;
u64 gicc_gicv = 0;
u64 gicc_gich = 0;
u64 gicc_gicr_base = 0;
u64 gicc_phys_base = 0;
u32 gicc_perf_gsiv = 0;
u64 gicc_mpidr;
u32 gicc_vgic_maint_irq = 0;
int addr_index;
fdt_addr_t addr;
int ret;
struct irq req_irq;
cpu_plat = dev_get_parent_plat(dev);
if (!cpu_plat)
return 0;
ret = irq_get_interrupt_parent(dev, &gic);
if (ret) {
log_err("%s: Failed to find interrupt parent for %s\n",
__func__, dev->name);
return -ENODEV;
}
addr_index = 1;
if (device_is_compatible(gic, "arm,gic-v3")) {
addr = dev_read_addr_index(gic, addr_index++);
if (addr != FDT_ADDR_T_NONE)
gicc_gicr_base = addr;
}
addr = dev_read_addr_index(gic, addr_index++);
if (addr != FDT_ADDR_T_NONE)
gicc_phys_base = addr;
addr = dev_read_addr_index(gic, addr_index++);
if (addr != FDT_ADDR_T_NONE)
gicc_gich = addr;
addr = dev_read_addr_index(gic, addr_index++);
if (addr != FDT_ADDR_T_NONE)
gicc_gicv = addr;
ret = irq_get_by_index(gic, 0, &req_irq);
if (!ret)
gicc_vgic_maint_irq = req_irq.id;
gicc_mpidr = dev_read_u64_default(dev, "reg", 0);
if (!gicc_mpidr)
gicc_mpidr = dev_read_u32_default(dev, "reg", 0);
/*
* gicc_vgic_maint_irq and gicc_gicv are the same for every CPU
*/
gicc = ctx->current;
acpi_write_madt_gicc(gicc,
dev_seq(dev),
gicc_perf_gsiv, /* FIXME: needs a PMU driver */
gicc_phys_base,
gicc_gicv,
gicc_gich,
gicc_vgic_maint_irq,
gicc_gicr_base,
gicc_mpidr,
0); /* FIXME: Not defined in DT */
acpi_inc(ctx, gicc->length);
return 0;
}
struct acpi_ops armv8_cpu_acpi_ops = {
.fill_ssdt = armv8_cpu_fill_ssdt,
.fill_madt = armv8_cpu_fill_madt,
};
#endif

10
drivers/cpu/armv8_cpu.h
View File

@@ -18,4 +18,14 @@
*/
int armv8_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx);
/**
* armv8_cpu_fill_madt() - Fill the MADT
* Parses the FDT and writes the MADT subtables.
*
* @dev: cpu device to generate ACPI tables for
* @ctx: ACPI context pointer
* @return: 0 if OK, or a negative error code.
*/
int armv8_cpu_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx);
#endif