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driver: clk: tegra: partially support PLL clocks

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Return PLL id into struct clk if PLL is parsed from device
tree instead of throwing an error. Allow requesting PLL
clock rate via get_rate op.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
This commit is contained in:
Svyatoslav Ryhel
2024-12-13 16:53:18 +02:00
committed by Tom Rini
parent e46fe0daf3
commit 1db256a347
1 changed files with 38 additions and 9 deletions
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47
drivers/clk/tegra/tegra-car-clk.c
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@@ -10,6 +10,9 @@
#include <asm/arch/clock.h>
#include <asm/arch-tegra/clk_rst.h>
#define TEGRA_CAR_CLK_PLL BIT(0)
#define TEGRA_CAR_CLK_PERIPH BIT(1)
static int tegra_car_clk_request(struct clk *clk)
{
debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
@@ -20,24 +23,41 @@ static int tegra_car_clk_request(struct clk *clk)
* varies per SoC) are the peripheral clocks, which use a numbering
* scheme that matches HW registers 1:1. There are other clock IDs
* beyond this that are assigned arbitrarily by the Tegra CAR DT
* binding. Due to the implementation of this driver, it currently
* only supports the peripheral IDs.
* binding.
*/
if (clk->id >= PERIPH_ID_COUNT)
return -EINVAL;
if (clk->id < PERIPH_ID_COUNT) {
clk->data |= TEGRA_CAR_CLK_PERIPH;
return 0;
}
return 0;
/* If check for periph failed, then check for PLL clock id */
int id = clk_id_to_pll_id(clk->id);
if (clock_id_is_pll(id)) {
clk->id = id;
clk->data |= TEGRA_CAR_CLK_PLL;
return 0;
}
return -EINVAL;
}
static ulong tegra_car_clk_get_rate(struct clk *clk)
{
enum clock_id parent;
debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
clk->id);
parent = clock_get_periph_parent(clk->id);
return clock_get_periph_rate(clk->id, parent);
if (clk->data & TEGRA_CAR_CLK_PLL)
return clock_get_rate(clk->id);
if (clk->data & TEGRA_CAR_CLK_PERIPH) {
enum clock_id parent;
parent = clock_get_periph_parent(clk->id);
return clock_get_periph_rate(clk->id, parent);
}
return -1U;
}
static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
@@ -47,6 +67,9 @@ static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
clk->dev, clk->id);
if (clk->data & TEGRA_CAR_CLK_PLL)
return 0;
parent = clock_get_periph_parent(clk->id);
return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL);
}
@@ -56,6 +79,9 @@ static int tegra_car_clk_enable(struct clk *clk)
debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
clk->id);
if (clk->data & TEGRA_CAR_CLK_PLL)
return 0;
clock_enable(clk->id);
return 0;
@@ -66,6 +92,9 @@ static int tegra_car_clk_disable(struct clk *clk)
debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
clk->id);
if (clk->data & TEGRA_CAR_CLK_PLL)
return 0;
clock_disable(clk->id);
return 0;