85xx: Added various P1012/P1013/P1021/P1022 defines
There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list * Added number of LAWs for P1012/P1013/P1021/P1022 * Set CONFIG_MAX_CPUS to 2 for P1021/P1022 * PCI port config Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@@ -1,5 +1,5 @@
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/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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* Copyright 2009-2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@@ -41,6 +41,7 @@
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#endif
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#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \
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defined(CONFIG_P1021) || defined(CONFIG_P1022) || \
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defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
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#define CONFIG_MAX_CPUS 2
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#elif defined(CONFIG_PPC_P4080)
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@@ -1035,8 +1035,16 @@
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#define SVR_8572_E 0x80E800
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#define SVR_P1011 0x80E500
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#define SVR_P1011_E 0x80ED00
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#define SVR_P1012 0x80E501
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#define SVR_P1012_E 0x80ED01
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#define SVR_P1013 0x80E700
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#define SVR_P1013_E 0x80EF00
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#define SVR_P1020 0x80E400
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#define SVR_P1020_E 0x80EC00
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#define SVR_P1021 0x80E401
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#define SVR_P1021_E 0x80EC01
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#define SVR_P1022 0x80E600
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#define SVR_P1022_E 0x80EE00
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#define SVR_P2010 0x80E300
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#define SVR_P2010_E 0x80EB00
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#define SVR_P2020 0x80E200
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