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clk: zynqmp: Add gem rx and tsu clocks to return register

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Add gem_tsu and gem0_rx till gem3_rx to return proper register from
zynqmp_clk_get_register. Otherwise firmware won't be able to set clock
for these due to incorrect register address.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20230720072859.3724-1-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
This commit is contained in:
Ashok Reddy Soma
2023-07-20 01:28:59 -06:00
committed by Michal Simek
parent 7a480fd995
commit 2a907542c7
1 changed files with 5 additions and 0 deletions
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5
drivers/clk/clk_zynqmp.c
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@@ -270,17 +270,22 @@ static u32 zynqmp_clk_get_register(enum zynqmp_clk id)
case usb3_dual_ref:
return CRL_APB_USB3_DUAL_REF_CTRL;
case gem_tsu_ref:
case gem_tsu:
return CRL_APB_GEM_TSU_REF_CTRL;
case gem0_tx:
case gem0_rx:
case gem0_ref:
return CRL_APB_GEM0_REF_CTRL;
case gem1_tx:
case gem1_rx:
case gem1_ref:
return CRL_APB_GEM1_REF_CTRL;
case gem2_tx:
case gem2_rx:
case gem2_ref:
return CRL_APB_GEM2_REF_CTRL;
case gem3_tx:
case gem3_rx:
case gem3_ref:
return CRL_APB_GEM3_REF_CTRL;
case usb0_bus_ref: