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arm64: dts: rockchip: Add HDMI0 node to rk3588

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Add support for the HDMI0 output port found on RK3588 SoC.

Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20241019-rk3588-hdmi0-dt-v2-1-466cd80e8ff9@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: d7bb71e69f58c1b3665a9f926bf8d3855111bf8e ]

(cherry picked from commit a839348380c2072e00a26bbdb80744982fe04c56)
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Cristian Ciocaltea
2025-01-04 01:57:02 +00:00
committed by Tom Rini
parent d113d47976
commit 2cbffc1579
1 changed files with 41 additions and 0 deletions
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41
dts/upstream/src/arm64/rockchip/rk3588-base.dtsi
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@@ -1370,6 +1370,47 @@
status = "disabled";
};
hdmi0: hdmi@fde80000 {
compatible = "rockchip,rk3588-dw-hdmi-qp";
reg = <0x0 0xfde80000 0x0 0x20000>;
clocks = <&cru PCLK_HDMITX0>,
<&cru CLK_HDMITX0_EARC>,
<&cru CLK_HDMITX0_REF>,
<&cru MCLK_I2S5_8CH_TX>,
<&cru CLK_HDMIHDP0>,
<&cru HCLK_VO1>;
clock-names = "pclk", "earc", "ref", "aud", "hdp", "hclk_vo1";
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "avp", "cec", "earc", "main", "hpd";
phys = <&hdptxphy_hdmi0>;
pinctrl-names = "default";
pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd
&hdmim0_tx0_scl &hdmim0_tx0_sda>;
power-domains = <&power RK3588_PD_VO1>;
resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>;
reset-names = "ref", "hdp";
rockchip,grf = <&sys_grf>;
rockchip,vo-grf = <&vo1_grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
hdmi0_in: port@0 {
reg = <0>;
};
hdmi0_out: port@1 {
reg = <1>;
};
};
};
qos_gpu_m0: qos@fdf35000 {
compatible = "rockchip,rk3588-qos", "syscon";
reg = <0x0 0xfdf35000 0x0 0x20>;