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Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze

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This commit is contained in:
Tom Rini
2015-01-26 06:42:15 -05:00
parent 03cae7261e a2425e6207
commit 306df2c824
11 changed files with 137 additions and 40 deletions
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1
arch/arm/cpu/armv7/zynq/Makefile
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@@ -13,4 +13,5 @@ obj-y += cpu.o
obj-y += ddrc.o
obj-y += slcr.o
obj-y += clk.o
obj-y += lowlevel_init.o
obj-$(CONFIG_SPL_BUILD) += spl.o

7
arch/arm/cpu/armv7/zynq/config.mk Normal file
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@@ -0,0 +1,7 @@
#
# Copyright (C) 2013 - 2015 Xilinx, Inc. All rights reserved.
#
# SPDX-License-Identifier: GPL-2.0
#
# Allow NEON instructions (needed for lowlevel_init.S with GNU toolchain)
PLATFORM_RELFLAGS += -mfpu=neon

4
arch/arm/cpu/armv7/zynq/cpu.c
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@@ -10,10 +10,6 @@
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
void lowlevel_init(void)
{
}
#define ZYNQ_SILICON_VER_MASK 0xF0000000
#define ZYNQ_SILICON_VER_SHIFT 28

2
arch/arm/cpu/armv7/zynq/ddrc.c
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@@ -42,6 +42,8 @@ void zynq_ddrc_init(void)
*/
/* cppcheck-suppress nullPointer */
memset((void *)0, 0, 1 * 1024 * 1024);
gd->ram_size /= 2;
} else {
puts("ECC disabled ");
}

26
arch/arm/cpu/armv7/zynq/lowlevel_init.S Normal file
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@@ -0,0 +1,26 @@
/*
* Copyright (C) 2013 Xilinx, Inc. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
ENTRY(lowlevel_init)
/* Enable the the VFP */
mrc p15, 0, r1, c1, c0, 2
orr r1, r1, #(0x3 << 20)
orr r1, r1, #(0x3 << 20)
mcr p15, 0, r1, c1, c0, 2
isb
fmrx r1, FPEXC
orr r1,r1, #(1<<30)
fmxr FPEXC, r1
/* Move back to caller */
mov pc, lr
ENDPROC(lowlevel_init)

2
arch/arm/cpu/armv7/zynq/slcr.c
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@@ -132,7 +132,7 @@ void zynq_slcr_devcfg_disable(void)
zynq_slcr_unlock();
/* Disable AXI interface by asserting FPGA resets */
writel(0xFFFFFFFF, &slcr_base->fpga_rst_ctrl);
writel(0xF, &slcr_base->fpga_rst_ctrl);
/* Set Level Shifters DT618760 */
writel(0xA, &slcr_base->lvl_shftr_en);

9
arch/arm/cpu/armv7/zynq/spl.c
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@@ -43,12 +43,21 @@ u32 spl_boot_device(void)
mode = BOOT_DEVICE_SPI;
break;
#endif
case ZYNQ_BM_NAND:
mode = BOOT_DEVICE_NAND;
break;
case ZYNQ_BM_NOR:
mode = BOOT_DEVICE_NOR;
break;
#ifdef CONFIG_SPL_MMC_SUPPORT
case ZYNQ_BM_SD:
puts("mmc boot\n");
mode = BOOT_DEVICE_MMC1;
break;
#endif
case ZYNQ_BM_JTAG:
mode = BOOT_DEVICE_RAM;
break;
default:
puts("Unsupported boot mode selected\n");
hang();

5
arch/arm/include/asm/arch-zynq/hardware.h
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@@ -21,6 +21,9 @@
#define ZYNQ_I2C_BASEADDR1 0xE0005000
#define ZYNQ_SPI_BASEADDR0 0xE0006000
#define ZYNQ_SPI_BASEADDR1 0xE0007000
#define ZYNQ_QSPI_BASEADDR 0xE000D000
#define ZYNQ_SMC_BASEADDR 0xE000E000
#define ZYNQ_NAND_BASEADDR 0xE1000000
#define ZYNQ_DDRC_BASEADDR 0xF8006000
#define ZYNQ_EFUSE_BASEADDR 0xF800D000
#define ZYNQ_USB_BASEADDR0 0xE0002000
@@ -28,7 +31,9 @@
/* Bootmode setting values */
#define ZYNQ_BM_MASK 0x7
#define ZYNQ_BM_QSPI 0x1
#define ZYNQ_BM_NOR 0x2
#define ZYNQ_BM_NAND 0x4
#define ZYNQ_BM_SD 0x5
#define ZYNQ_BM_JTAG 0x0