phy: marvell: add support for SFI1

In CP115, comphy4 can be configured into SFI port1
(in addition to SFI0). This patch adds the option
described above.

In addition, rename all existing SFI/XFI references:
COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0

No functional change for exsiting configuration.

Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
This commit is contained in:
Igal Liberman
2018-05-14 11:20:54 +03:00
committed by Stefan Roese
parent a007f23626
commit 341e548eb8
10 changed files with 26 additions and 22 deletions

View File

@@ -41,7 +41,7 @@ static const char *get_type_string(u32 type)
"UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3",
"SATA0", "SATA1", "SGMII0", "SGMII1", "SGMII2",
"USB3", "USB3_HOST0", "USB3_HOST1",
"USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI", "AP",
"USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI0", "SFI1", "AP",
"IGNORE"
};

View File

@@ -109,10 +109,11 @@ int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg,
u32 lane)
{
int ret;
u32 type = ptr_chip_cfg->comphy_map_data[lane].type;
debug_enter();
if (ptr_chip_cfg->comphy_map_data[lane].type != COMPHY_TYPE_SFI) {
if (type != COMPHY_TYPE_SFI0 && type != COMPHY_TYPE_SFI1) {
pr_err("Comphy %d isn't configured to SFI\n", lane);
return 0;
}
@@ -630,13 +631,14 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
break;
case COMPHY_TYPE_SFI:
mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE,
COMPHY_UNIT_ID0,
case COMPHY_TYPE_SFI0:
case COMPHY_TYPE_SFI1:
/* Calculate SFI id */
id = ptr_comphy_map->type - COMPHY_TYPE_SFI0;
mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, id,
ptr_comphy_map->speed);
ret = comphy_smc(MV_SIP_COMPHY_POWER_ON,
ptr_chip_cfg->comphy_base_addr, lane,
mode);
ptr_chip_cfg->comphy_base_addr, lane, mode);
break;
case COMPHY_TYPE_RXAUI0:
case COMPHY_TYPE_RXAUI1: