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Merge tag 'v2022.04-rc5' into next

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Prepare v2022.04-rc5
This commit is contained in:
Tom Rini
2022-03-28 12:36:49 -04:00
parent 7f0826c169 e893e8ea6a
commit 34d2b7f203
146 changed files with 2475 additions and 553 deletions
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16
board/google/gru/Kconfig
View File

@@ -13,3 +13,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif
if TARGET_CHROMEBOOK_KEVIN
config SYS_BOARD
default "gru"
config SYS_VENDOR
default "google"
config SYS_CONFIG_NAME
default "gru"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
endif

8
board/google/gru/MAINTAINERS
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@@ -4,3 +4,11 @@ S: Maintained
F: board/google/gru/
F: include/configs/gru.h
F: configs/chromebook_bob_defconfig
CHROMEBOOK KEVIN BOARD
M: Simon Glass <sjg@chromium.org>
M: Alper Nebi Yasak <alpernebiyasak@gmail.com>
S: Maintained
F: board/google/gru/
F: include/configs/gru.h
F: configs/chromebook_kevin_defconfig

54
board/google/gru/gru.c
View File

@@ -6,6 +6,17 @@
#include <common.h>
#include <dm.h>
#include <init.h>
#include <syscon.h>
#include <asm/io.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch-rockchip/grf_rk3399.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/arch-rockchip/misc.h>
#define GRF_IO_VSEL_BT656_SHIFT 0
#define GRF_IO_VSEL_AUDIO_SHIFT 1
#define PMUGRF_CON0_VSEL_SHIFT 8
#define PMUGRF_CON0_VOL_SHIFT 9
#ifdef CONFIG_SPL_BUILD
/* provided to defeat compiler optimisation in board_init_f() */
@@ -15,7 +26,7 @@ void gru_dummy_function(int i)
int board_early_init_f(void)
{
# ifdef CONFIG_TARGET_CHROMEBOOK_BOB
# if defined(CONFIG_TARGET_CHROMEBOOK_BOB) || defined(CONFIG_TARGET_CHROMEBOOK_KEVIN)
int sum, i;
/*
@@ -54,3 +65,44 @@ int board_early_init_r(void)
return 0;
}
#endif
static void setup_iodomain(void)
{
struct rk3399_grf_regs *grf =
syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
struct rk3399_pmugrf_regs *pmugrf =
syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
/* BT656 and audio is in 1.8v domain */
rk_setreg(&grf->io_vsel, (1 << GRF_IO_VSEL_BT656_SHIFT |
1 << GRF_IO_VSEL_AUDIO_SHIFT));
/*
* Set GPIO1 1.8v/3.0v source select to PMU1830_VOL
* and explicitly configure that PMU1830_VOL to be 1.8V
*/
rk_setreg(&pmugrf->soc_con0, (1 << PMUGRF_CON0_VSEL_SHIFT |
1 << PMUGRF_CON0_VOL_SHIFT));
}
int misc_init_r(void)
{
const u32 cpuid_offset = 0x7;
const u32 cpuid_length = 0x10;
u8 cpuid[cpuid_length];
int ret;
setup_iodomain();
ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
if (ret)
return ret;
ret = rockchip_cpuid_set(cpuid, cpuid_length);
if (ret)
return ret;
ret = rockchip_setup_macaddr();
return ret;
}