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power: rename stpmu1 to official name stpmic1

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Alignment with kernel driver name & binding
introduced by https://patchwork.kernel.org/cover/10761943/
to use the final marketing name = STPMIC1.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
This commit is contained in:
Patrick Delaunay
2019-02-04 11:26:17 +01:00
parent d46c22b3fd
commit 42f01aacfd
15 changed files with 436 additions and 434 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
board/st/stm32mp1/README
View File

@@ -28,7 +28,7 @@ Everything is supported in Linux but U-Boot is limited to:
And the necessary drivers
1. I2C
2. STPMU1 (PMIC and regulator)
2. STPMIC1 (PMIC and regulator)
3. Clock, Reset, Sysreset
4. Fuse
@@ -70,10 +70,10 @@ Each board is configurated only with the associated device tree.
You need to select the appropriate device tree for your board,
the supported device trees for stm32mp157 are:
+ ev1: eval board with pmic stpmu1 (ev1 = mother board + daughter ed1)
+ ev1: eval board with pmic stpmic1 (ev1 = mother board + daughter ed1)
dts: stm32mp157c-ev1
+ ed1: daughter board with pmic stpmu1
+ ed1: daughter board with pmic stpmic1
dts: stm32mp157c-ed1
5. Build Procedure

45
board/st/stm32mp1/board.c
View File

@@ -37,64 +37,65 @@ void board_debug_uart_init(void)
}
#endif
#ifdef CONFIG_PMIC_STPMU1
#ifdef CONFIG_PMIC_STPMIC1
int board_ddr_power_init(void)
{
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_PMIC,
DM_GET_DRIVER(pmic_stpmu1), &dev);
DM_GET_DRIVER(pmic_stpmic1), &dev);
if (ret)
/* No PMIC on board */
return 0;
/* Set LDO3 to sync mode */
ret = pmic_reg_read(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3));
/* VTT = Set LDO3 to sync mode */
ret = pmic_reg_read(dev, STPMIC1_LDOX_CTRL_REG(STPMIC1_LDO3));
if (ret < 0)
return ret;
ret &= ~STPMU1_LDO3_MODE;
ret &= ~STPMU1_LDO12356_OUTPUT_MASK;
ret |= STPMU1_LDO3_DDR_SEL << STPMU1_LDO12356_OUTPUT_SHIFT;
ret &= ~STPMIC1_LDO3_MODE;
ret &= ~STPMIC1_LDO12356_OUTPUT_MASK;
ret |= STPMIC1_LDO3_DDR_SEL << STPMIC1_LDO12356_OUTPUT_SHIFT;
ret = pmic_reg_write(dev, STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
ret = pmic_reg_write(dev, STPMIC1_LDOX_CTRL_REG(STPMIC1_LDO3),
ret);
if (ret < 0)
return ret;
/* Set BUCK2 to 1.35V */
/* VDD_DDR = Set BUCK2 to 1.35V */
ret = pmic_clrsetbits(dev,
STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
STPMU1_BUCK_OUTPUT_MASK,
STPMU1_BUCK2_1350000V);
STPMIC1_BUCKX_CTRL_REG(STPMIC1_BUCK2),
STPMIC1_BUCK_OUTPUT_MASK,
STPMIC1_BUCK2_1350000V);
if (ret < 0)
return ret;
/* Enable BUCK2 and VREF */
/* Enable VDD_DDR = BUCK2 */
ret = pmic_clrsetbits(dev,
STPMU1_BUCKX_CTRL_REG(STPMU1_BUCK2),
STPMU1_BUCK_EN, STPMU1_BUCK_EN);
STPMIC1_BUCKX_CTRL_REG(STPMIC1_BUCK2),
STPMIC1_BUCK_EN, STPMIC1_BUCK_EN);
if (ret < 0)
return ret;
mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
ret = pmic_clrsetbits(dev, STPMU1_VREF_CTRL_REG,
STPMU1_VREF_EN, STPMU1_VREF_EN);
/* Enable VREF */
ret = pmic_clrsetbits(dev, STPMIC1_VREF_CTRL_REG,
STPMIC1_VREF_EN, STPMIC1_VREF_EN);
if (ret < 0)
return ret;
mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
/* Enable LDO3 */
ret = pmic_clrsetbits(dev,
STPMU1_LDOX_CTRL_REG(STPMU1_LDO3),
STPMU1_LDO_EN, STPMU1_LDO_EN);
STPMIC1_LDOX_CTRL_REG(STPMIC1_LDO3),
STPMIC1_LDO_EN, STPMIC1_LDO_EN);
if (ret < 0)
return ret;
mdelay(STPMU1_DEFAULT_START_UP_DELAY_MS);
mdelay(STPMIC1_DEFAULT_START_UP_DELAY_MS);
return 0;
}

10
board/st/stm32mp1/spl.c
View File

@@ -17,16 +17,16 @@
void spl_board_init(void)
{
/* Keep vdd on during the reset cycle */
#if defined(CONFIG_PMIC_STPMU1) && defined(CONFIG_SPL_POWER_SUPPORT)
#if defined(CONFIG_PMIC_STPMIC1) && defined(CONFIG_SPL_POWER_SUPPORT)
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_PMIC,
DM_GET_DRIVER(pmic_stpmu1), &dev);
DM_GET_DRIVER(pmic_stpmic1), &dev);
if (!ret)
pmic_clrsetbits(dev,
STPMU1_MASK_RESET_BUCK,
STPMU1_MASK_RESET_BUCK3,
STPMU1_MASK_RESET_BUCK3);
STPMIC1_MASK_RESET_BUCK,
STPMIC1_MASK_RESET_BUCK3,
STPMIC1_MASK_RESET_BUCK3);
#endif
}