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Patch by Josef Wagner, 04 Jun 2004:

Browse Source 
- DDR Ram support for PM520 (MPC5200)
- support for different flash types (PM520)
- USB / IDE / CF-Card / DiskOnChip support for PM520
- 8 bit boot rom support for PM520/CE520
- Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245)
- I2C and RTC support for CPC45
- support of new flash type (28F160C3T) for CPC45
This commit is contained in:
wdenk
2004-06-19 21:19:10 +00:00
parent 46a414dc12
commit 49822e23a0
26 changed files with 1714 additions and 1390 deletions
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48
board/mx1ads/Makefile
View File

@@ -1,28 +1,26 @@
#/*
#* board/mx1ads/Makefile
#*
#* (c) Copyright 2004
#* Techware Information Technology, Inc.
#* http://www.techware.com.tw/
#*
#* Ming-Len Wu <minglen_wu@techware.com.tw>
#*
#* This program is free software; you can redistribute it and/or
#* modify it under the terms of the GNU General Public License as
#* published by the Free Software Foundation; either version 2 of
#* the License, or (at your option) any later version.
#*
#* This program is distributed in the hope that it will be useful,
#* but WITHOUT ANY WARRANTY; without even the implied warranty of
#* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
#* GNU General Public License for more details.
#*
#* You should have received a copy of the GNU General Public License
#* along with this program; if not, write to the Free Software
#* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
#* MA 02111-1307 USA
#*/
#
# board/mx1ads/Makefile
#
# (c) Copyright 2004
# Techware Information Technology, Inc.
# http://www.techware.com.tw/
#
# Ming-Len Wu <minglen_wu@techware.com.tw>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
include $(TOPDIR)/config.mk

49
board/mx1ads/config.mk
View File

@@ -1,28 +1,25 @@
#/*
#* board/mx1ads/config.mk
#*
#* (c) Copyright 2004
#* Techware Information Technology, Inc.
#* http://www.techware.com.tw/
#*
#* Ming-Len Wu <minglen_wu@techware.com.tw>
#*
#* This program is free software; you can redistribute it and/or
#* modify it under the terms of the GNU General Public License as
#* published by the Free Software Foundation; either version 2 of
#* the License, or (at your option) any later version.
#*
#* This program is distributed in the hope that it will be useful,
#* but WITHOUT ANY WARRANTY; without even the implied warranty of
#* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
#* GNU General Public License for more details.
#*
#* You should have received a copy of the GNU General Public License
#* along with this program; if not, write to the Free Software
#* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
#* MA 02111-1307 USA
#*/
#
# board/mx1ads/config.mk
#
# (c) Copyright 2004
# Techware Information Technology, Inc.
# http://www.techware.com.tw/
#
# Ming-Len Wu <minglen_wu@techware.com.tw>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
TEXT_BASE = 0x08400000

9
board/mx1ads/memsetup.S
View File

@@ -1,6 +1,6 @@
/*
* board/mx1ads/memsetup.S
*
*
* (c) Copyright 2004
* Techware Information Technology, Inc.
* http://www.techware.com.tw/
@@ -49,7 +49,7 @@ memsetup:
/* Issue Precharge All Commad */
ldr r3, =0x8200000
ldr r2, [r3]
/* Set AutoRefresh Command */
ldr r3, =0xA2120200
str r3, [r1]
@@ -64,11 +64,11 @@ memsetup:
ldr r2, [r3]
ldr r2, [r3]
ldr r2, [r3]
/* Set Mode Register */
ldr r3, =0xB2120200
str r3, [r1]
/* Issue Mode Register Command */
ldr r3, =0x08111800 /* Mode Register Value */
ldr r2, [r3]
@@ -79,4 +79,3 @@ memsetup:
/* everything is fine now */
mov pc, lr

41
board/mx1ads/mx1ads.c
View File

@@ -1,6 +1,6 @@
/*
* board/mx1ads/mx1ads.c
*
*
* (c) Copyright 2004
* Techware Information Technology, Inc.
* http://www.techware.com.tw/
@@ -61,7 +61,7 @@ static inline void delay (unsigned long loops) {
"bne 1b":"=r" (loops):"0" (loops));
}
#endif
#endif
/*
* Miscellaneous platform dependent initialisations
@@ -76,7 +76,7 @@ void SetAsynchMode(void) {
"mcr p15,0,r0,c1,c0,0 \n"
);
}
static u32 mc9328sid;
int board_init (void) {
@@ -88,16 +88,13 @@ int board_init (void) {
mc9328sid = MX1_SIDR;
MX1_GPCR = 0x000003AB; /* I/O pad driving strength */
/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
/* MX1_CS1L = 0x11110601; */
MX1_MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
/* MX1_MPCTL0 = 0x003f1437; *//* setting for 192 MHz MCU PLL CLK */
/* MX1_MPCTL0 = 0x003f1437; */ /* setting for 192 MHz MCU PLL CLK */
/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
* BCLK divider to 2 (i.e. BCLK to 48 MHz)
@@ -108,13 +105,13 @@ int board_init (void) {
MX1_CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
/* setup cs4 for cs8900 ethernet */
MX1_CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
MX1_CS4L = 0x00001501;
MX1_GIUS_A &= 0xFF3FFFFF;
MX1_GPR_A &= 0xFF3FFFFF;
tmp = *(unsigned int *)(0x1500000C);
tmp = *(unsigned int *)(0x1500000C);
@@ -135,9 +132,9 @@ int board_init (void) {
/* set PERCLKs */
MX1_PCDR = 0x00000055; /* set PERCLKS */
/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
* PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
* PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
* all sources selected as normal interrupt
*/
MX1_INTTYPEH = 0;
@@ -154,24 +151,24 @@ int board_late_init(void) {
switch (mc9328sid) {
case 0x0005901d :
printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",mc9328sid);
printf ("MX1ADS board with MC9328 MX1 (0L44N), Silicon ID 0x%08x \n\n",mc9328sid);
break;
case 0x04d4c01d :
printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",mc9328sid);
printf ("MX1ADS board with MC9328 MXL (1L45N), Silicon ID 0x%08x \n\n",mc9328sid);
break;
case 0x00d4c01d :
printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",mc9328sid);
printf ("MX1ADS board with MC9328 MXL (2L45N), Silicon ID 0x%08x \n\n",mc9328sid);
break;
default :
printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid);
printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid);
break;
}
return 0;
}
}
int dram_init (void) {
DECLARE_GLOBAL_DATA_PTR;

46
board/mx1ads/syncflash.c
View File

@@ -1,6 +1,6 @@
/*
* board/mx1ads/syncflash.c
*
*
* (c) Copyright 2004
* Techware Information Technology, Inc.
* http://www.techware.com.tw/
@@ -61,7 +61,7 @@ u32 SF_SR(void) {
reg_SFCTL = CMD_PROGRAM;
tmp = __REG(CFG_FLASH_BASE);
reg_SFCTL = CMD_NORMAL;
reg_SFCTL = CMD_LCR; /* Activate LCR Mode */
@@ -97,7 +97,7 @@ void SF_PrechargeAll(void) {
u32 tmp;
reg_SFCTL = CMD_PREC; /* Set Precharge Command */
tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
}
@@ -105,7 +105,7 @@ void SF_PrechargeAll(void) {
void SF_Normal(void) {
SF_PrechargeAll();
reg_SFCTL = CMD_NORMAL;
}
@@ -118,10 +118,10 @@ void SF_Erase(u32 RowAddress) {
reg_SFCTL = CMD_PREC;
tmp = __REG(RowAddress);
reg_SFCTL = CMD_LCR; /* Set LCR mode */
__REG(RowAddress + LCR_ERASE_CONFIRM) = 0; /* Issue Erase Setup Command */
reg_SFCTL = CMD_NORMAL; /* return to Normal mode */
__REG(RowAddress) = 0xD0D0D0D0; /* Confirm */
@@ -134,7 +134,7 @@ void SF_NvmodeErase(void) {
reg_SFCTL = CMD_LCR; /* Set to LCR mode */
__REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0; /* Issue Erase Nvmode Reg Command */
reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
__REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0; /* Confirm */
@@ -146,7 +146,7 @@ void SF_NvmodeWrite(void) {
reg_SFCTL = CMD_LCR; /* Set to LCR mode */
__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0; /* Issue Program Nvmode reg command */
reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */
@@ -168,11 +168,11 @@ ulong flash_init(void) {
tmp = __REG(MODE_REG_VAL); /* Issue Load Mode Register Command */
SF_Normal();
i = 0;
flash_info[i].flash_id = FLASH_MAN_MT | FLASH_MT28S4M16LC;
flash_info[i].size = FLASH_BANK_SIZE;
flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
@@ -181,7 +181,7 @@ ulong flash_init(void) {
for (j = 0; j < flash_info[i].sector_count; j++) {
flash_info[i].start[j] = CFG_FLASH_BASE + j * 0x00100000;
}
flash_protect(FLAG_PROTECT_SET,
CFG_FLASH_BASE,
CFG_FLASH_BASE + monitor_flash_len - 1,
@@ -208,8 +208,8 @@ void flash_print_info (flash_info_t *info) {
printf("Unknown Vendor ");
break;
}
switch (info->flash_id & FLASH_TYPEMASK) {
case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
@@ -226,13 +226,13 @@ void flash_print_info (flash_info_t *info) {
printf(" Sector Start Addresses: ");
for (i = 0; i < info->sector_count; i++) {
if ((i % 5) == 0)
if ((i % 5) == 0)
printf ("\n ");
printf (" %08lX%s", info->start[i],
info->protect[i] ? " (RO)" : " ");
}
printf ("\n");
}
@@ -248,19 +248,19 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) {
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
if ((s_first < 0) || (s_first > s_last))
if ((s_first < 0) || (s_first > s_last))
return ERR_INVAL;
if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
return ERR_UNKNOWN_FLASH_VENDOR;
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect])
if (info->protect[sect])
prot++;
}
if (prot) {
printf("protected!\n");
return ERR_PROTECTED;
@@ -279,7 +279,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) {
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last && !ctrlc(); sect++) {
printf("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
@@ -307,8 +307,6 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) {
return rc;
}
/*-----------------------------------------------------------------------
* Copy memory to flash.
*/
@@ -316,7 +314,7 @@ int flash_erase (flash_info_t *info, int s_first, int s_last) {
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
int i;
for(i = 0; i < cnt; i += 4) {
for(i = 0; i < cnt; i += 4) {
SF_PrechargeAll();
@@ -327,6 +325,6 @@ int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
}
SF_Normal();
return ERR_OK;
}

2
board/mx1ads/u-boot.lds
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@@ -1,6 +1,6 @@
/*
* board/mx1ads/u-boot.lds
*
*
* (c) Copyright 2004
* Techware Information Technology, Inc.
* http://www.techware.com.tw/