mpc83xx: Add the support of MPC8315E SoC
The MPC8315E SoC including e300c3 core and new IP blocks, such as TDM, PCI Express and SATA controller. Signed-off-by: Dave Liu <daveliu@freescale.com>
This commit is contained in:
Dave Liu
Kim Phillips
@@ -102,6 +102,10 @@
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#define SPR_8313_REV10 0x80B10010
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#define SPR_8311E_REV10 0x80B20010
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#define SPR_8311_REV10 0x80B30010
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#define SPR_8315E_REV10 0x80B40010
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#define SPR_8315_REV10 0x80B50010
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#define SPR_8314E_REV10 0x80B60010
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#define SPR_8314_REV10 0x80B70010
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#define SPR_8379E_REV10 0x80C20010
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#define SPR_8379_REV10 0x80C30010
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@@ -220,8 +224,8 @@
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#define SICRL_URT_CTPR 0x06000000
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#define SICRL_IRQ_CTPR 0x00C00000
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#elif defined(CONFIG_MPC831X)
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/* SICRL bits - MPC831x specific */
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#elif defined(CONFIG_MPC8313)
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/* SICRL bits - MPC8313 specific */
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#define SICRL_LBC 0x30000000
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#define SICRL_UART 0x0C000000
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#define SICRL_SPI_A 0x03000000
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@@ -232,7 +236,7 @@
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#define SICRL_ETSEC1_A 0x0000000C
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#define SICRL_ETSEC2_A 0x00000003
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/* SICRH bits - MPC831x specific */
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/* SICRH bits - MPC8313 specific */
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#define SICRH_INTR_A 0x02000000
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#define SICRH_INTR_B 0x00C00000
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#define SICRH_IIC 0x00300000
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@@ -249,6 +253,41 @@
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#define SICRH_TSOBI1 0x00000002
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#define SICRH_TSOBI2 0x00000001
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#elif defined(CONFIG_MPC8315)
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/* SICRL bits - MPC8315 specific */
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#define SICRL_DMA_CH0 0xc0000000
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#define SICRL_DMA_SPI 0x30000000
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#define SICRL_UART 0x0c000000
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#define SICRL_IRQ4 0x02000000
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#define SICRL_IRQ5 0x01800000
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#define SICRL_IRQ6_7 0x00400000
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#define SICRL_IIC1 0x00300000
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#define SICRL_TDM 0x000c0000
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#define SICRL_TDM_SHARED 0x00030000
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#define SICRL_PCI_A 0x0000c000
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#define SICRL_ELBC_A 0x00003000
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#define SICRL_ETSEC1_A 0x000000c0
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#define SICRL_ETSEC1_B 0x00000030
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#define SICRL_ETSEC1_C 0x0000000c
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#define SICRL_TSEXPOBI 0x00000001
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/* SICRH bits - MPC8315 specific */
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#define SICRH_GPIO_0 0xc0000000
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#define SICRH_GPIO_1 0x30000000
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#define SICRH_GPIO_2 0x0c000000
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#define SICRH_GPIO_3 0x03000000
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#define SICRH_GPIO_4 0x00c00000
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#define SICRH_GPIO_5 0x00300000
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#define SICRH_GPIO_6 0x000c0000
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#define SICRH_GPIO_7 0x00030000
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#define SICRH_GPIO_8 0x0000c000
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#define SICRH_GPIO_9 0x00003000
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#define SICRH_GPIO_10 0x00000c00
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#define SICRH_GPIO_11 0x00000300
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#define SICRH_ETSEC2_A 0x000000c0
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#define SICRH_TSOBI1 0x00000002
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#define SICRH_TSOBI2 0x00000001
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#elif defined(CONFIG_MPC837X)
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/* SICRL bits - MPC837x specific */
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#define SICRL_USB_A 0xC0000000
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@@ -447,7 +486,7 @@
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#define HRCWL_CE_TO_PLL_1X30 0x0000001E
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#define HRCWL_CE_TO_PLL_1X31 0x0000001F
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#elif defined(CONFIG_MPC837X)
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#elif defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
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#define HRCWL_SVCOD 0x30000000
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#define HRCWL_SVCOD_SHIFT 28
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#define HRCWL_SVCOD_DIV_4 0x00000000
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@@ -556,7 +595,7 @@
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/* RSR - Reset Status Register
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*/
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#if defined(CONFIG_MPC837X)
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#if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
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#define RSR_RSTSRC 0xF0000000 /* Reset source */
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#define RSR_RSTSRC_SHIFT 28
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#else
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@@ -677,7 +716,7 @@
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#define SCCR_USBCM_2 0x00A00000
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#define SCCR_USBCM_3 0x00F00000
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#elif defined(CONFIG_MPC831X)
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#elif defined(CONFIG_MPC8313)
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/* TSEC1 bits are for TSEC2 as well */
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#define SCCR_TSEC1CM 0xc0000000
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#define SCCR_TSEC1CM_SHIFT 30
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@@ -697,6 +736,48 @@
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#define SCCR_USBDRCM_2 0x00200000
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#define SCCR_USBDRCM_3 0x00300000
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#elif defined(CONFIG_MPC8315)
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/* SCCR bits - MPC8315 specific */
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#define SCCR_TSEC1CM 0xc0000000
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#define SCCR_TSEC1CM_SHIFT 30
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#define SCCR_TSEC1CM_0 0x00000000
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#define SCCR_TSEC1CM_1 0x40000000
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#define SCCR_TSEC1CM_2 0x80000000
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#define SCCR_TSEC1CM_3 0xC0000000
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#define SCCR_TSEC2CM 0x30000000
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#define SCCR_TSEC2CM_SHIFT 28
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#define SCCR_TSEC2CM_0 0x00000000
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#define SCCR_TSEC2CM_1 0x10000000
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#define SCCR_TSEC2CM_2 0x20000000
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#define SCCR_TSEC2CM_3 0x30000000
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#define SCCR_USBDRCM 0x00300000
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#define SCCR_USBDRCM_SHIFT 20
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#define SCCR_USBDRCM_0 0x00000000
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#define SCCR_USBDRCM_1 0x00100000
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#define SCCR_USBDRCM_2 0x00200000
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#define SCCR_USBDRCM_3 0x00300000
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#define SCCR_PCIEXP1CM 0x00080000
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#define SCCR_PCIEXP2CM 0x00040000
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#define SCCR_SATA1CM 0x0000c000
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#define SCCR_SATA1CM_SHIFT 14
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#define SCCR_SATACM 0x0000f000
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#define SCCR_SATACM_SHIFT 8
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#define SCCR_SATACM_0 0x00000000
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#define SCCR_SATACM_1 0x00005000
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#define SCCR_SATACM_2 0x0000a000
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#define SCCR_SATACM_3 0x0000f000
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#define SCCR_TDMCM 0x000000c0
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#define SCCR_TDMCM_SHIFT 6
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#define SCCR_TDMCM_0 0x00000000
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#define SCCR_TDMCM_1 0x00000040
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#define SCCR_TDMCM_2 0x00000080
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#define SCCR_TDMCM_3 0x000000c0
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#elif defined(CONFIG_MPC837X)
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/* SCCR bits - MPC837x specific */
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#define SCCR_TSEC1CM 0xc0000000
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