mpc83xx: Add MPC8360EMDS basic board support
Add support for the Freescale MPC8360EMDS board. Includes DDR, DUART, Local Bus, PCI.
This commit is contained in:
Dave Liu
Kim Phillips
@@ -8,16 +8,6 @@
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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@@ -89,8 +79,30 @@
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/*
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* The device ID and revision numbers
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*/
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#define SPR_8349E_REV10 0x80300100
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#define SPR_8349E_REV11 0x80300101
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#define SPR_8349E_REV10 0x80300100
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#define SPR_8349_REV10 0x80310100
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#define SPR_8347E_REV10_TBGA 0x80320100
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#define SPR_8347_REV10_TBGA 0x80330100
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#define SPR_8347E_REV10_PBGA 0x80340100
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#define SPR_8347_REV10_PBGA 0x80350100
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#define SPR_8343E_REV10 0x80360100
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#define SPR_8343_REV10 0x80370100
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#define SPR_8349E_REV11 0x80300101
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#define SPR_8349_REV11 0x80310101
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#define SPR_8347E_REV11_TBGA 0x80320101
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#define SPR_8347_REV11_TBGA 0x80330101
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#define SPR_8347E_REV11_PBGA 0x80340101
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#define SPR_8347_REV11_PBGA 0x80350101
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#define SPR_8343E_REV11 0x80360101
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#define SPR_8343_REV11 0x80370101
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#define SPR_8360E_REV10 0x80480010
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#define SPR_8360_REV10 0x80490010
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#define SPR_8360E_REV11 0x80480011
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#define SPR_8360_REV11 0x80490011
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#define SPR_8360E_REV12 0x80480012
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#define SPR_8360_REV12 0x80490012
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/*
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* Base Registers & Option Registers
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@@ -122,9 +134,17 @@
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#define BR_MS_UPMA 0x00000080 /* UPMA */
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#define BR_MS_UPMB 0x000000A0 /* UPMB */
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#define BR_MS_UPMC 0x000000C0 /* UPMC */
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#if defined (CONFIG_MPC8360)
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#define BR_ATOM 0x0000000C
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#define BR_ATOM_SHIFT 2
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#endif
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#define BR_V 0x00000001
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#define BR_V_SHIFT 0
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#if defined (CONFIG_MPC8349)
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#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
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#elif defined (CONFIG_MPC8360)
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#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_ATOM|BR_V)
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#endif
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#define OR0 0x5004
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#define OR1 0x500C
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@@ -207,14 +227,21 @@
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#define HRCWH_PCI_AGENT 0x00000000
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#define HRCWH_PCI_HOST 0x80000000
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#if defined (CONFIG_MPC8349)
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#define HRCWH_32_BIT_PCI 0x00000000
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#define HRCWH_64_BIT_PCI 0x40000000
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#endif
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#define HRCWH_PCI1_ARBITER_DISABLE 0x00000000
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#define HRCWH_PCI1_ARBITER_ENABLE 0x20000000
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#if defined (CONFIG_MPC8349)
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#define HRCWH_PCI2_ARBITER_DISABLE 0x00000000
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#define HRCWH_PCI2_ARBITER_ENABLE 0x10000000
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#elif defined (CONFIG_MPC8360)
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#define HRCWH_PCICKDRV_DISABLE 0x00000000
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#define HRCWH_PCICKDRV_ENABLE 0x10000000
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#endif
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#define HRCWH_CORE_DISABLE 0x08000000
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#define HRCWH_CORE_ENABLE 0x00000000
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@@ -231,11 +258,14 @@
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#define HRCWH_ROM_LOC_DDR_SDRAM 0x00000000
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#define HRCWH_ROM_LOC_PCI1 0x00100000
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#if defined (CONFIG_MPC8349)
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#define HRCWH_ROM_LOC_PCI2 0x00200000
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#endif
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#define HRCWH_ROM_LOC_LOCAL_8BIT 0x00500000
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#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
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#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
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#if defined (CONFIG_MPC8349)
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#define HRCWH_TSEC1M_IN_RGMII 0x00000000
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#define HRCWH_TSEC1M_IN_RTBI 0x00004000
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#define HRCWH_TSEC1M_IN_GMII 0x00008000
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@@ -245,6 +275,12 @@
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#define HRCWH_TSEC2M_IN_RTBI 0x00001000
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#define HRCWH_TSEC2M_IN_GMII 0x00002000
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#define HRCWH_TSEC2M_IN_TBI 0x00003000
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#endif
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#if defined (CONFIG_MPC8360)
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#define HRCWH_SECONDARY_DDR_DISABLE 0x00000000
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#define HRCWH_SECONDARY_DDR_ENABLE 0x00000010
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#endif
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#define HRCWH_BIG_ENDIAN 0x00000000
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#define HRCWH_LITTLE_ENDIAN 0x00000008
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@@ -293,6 +329,47 @@
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#define HRCWL_CORE_TO_CSB_2_5X1 0x00050000
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#define HRCWL_CORE_TO_CSB_3X1 0x00060000
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#if defined (CONFIG_MPC8360)
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#define HRCWL_CE_PLL_VCO_DIV_4 0x00000000
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#define HRCWL_CE_PLL_VCO_DIV_8 0x00000040
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#define HRCWL_CE_PLL_VCO_DIV_2 0x00000080
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#define HRCWL_CE_PLL_DIV_1X1 0x00000000
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#define HRCWL_CE_PLL_DIV_2X1 0x00000020
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#define HRCWL_CE_TO_PLL_1X16_ 0x00000000
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#define HRCWL_CE_TO_PLL_1X2 0x00000002
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#define HRCWL_CE_TO_PLL_1X3 0x00000003
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#define HRCWL_CE_TO_PLL_1X4 0x00000004
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#define HRCWL_CE_TO_PLL_1X5 0x00000005
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#define HRCWL_CE_TO_PLL_1X6 0x00000006
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#define HRCWL_CE_TO_PLL_1X7 0x00000007
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#define HRCWL_CE_TO_PLL_1X8 0x00000008
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#define HRCWL_CE_TO_PLL_1X9 0x00000009
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#define HRCWL_CE_TO_PLL_1X10 0x0000000A
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#define HRCWL_CE_TO_PLL_1X11 0x0000000B
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#define HRCWL_CE_TO_PLL_1X12 0x0000000C
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#define HRCWL_CE_TO_PLL_1X13 0x0000000D
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#define HRCWL_CE_TO_PLL_1X14 0x0000000E
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#define HRCWL_CE_TO_PLL_1X15 0x0000000F
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#define HRCWL_CE_TO_PLL_1X16 0x00000010
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#define HRCWL_CE_TO_PLL_1X17 0x00000011
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#define HRCWL_CE_TO_PLL_1X18 0x00000012
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#define HRCWL_CE_TO_PLL_1X19 0x00000013
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#define HRCWL_CE_TO_PLL_1X20 0x00000014
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#define HRCWL_CE_TO_PLL_1X21 0x00000015
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#define HRCWL_CE_TO_PLL_1X22 0x00000016
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#define HRCWL_CE_TO_PLL_1X23 0x00000017
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#define HRCWL_CE_TO_PLL_1X24 0x00000018
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#define HRCWL_CE_TO_PLL_1X25 0x00000019
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#define HRCWL_CE_TO_PLL_1X26 0x0000001A
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#define HRCWL_CE_TO_PLL_1X27 0x0000001B
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#define HRCWL_CE_TO_PLL_1X28 0x0000001C
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#define HRCWL_CE_TO_PLL_1X29 0x0000001D
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#define HRCWL_CE_TO_PLL_1X30 0x0000001E
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#define HRCWL_CE_TO_PLL_1X31 0x0000001F
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#endif
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/*
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* LCRR - Clock Ratio Register (10.3.1.16)
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*/
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@@ -346,6 +423,7 @@
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| SCCR_TSEC2CM_3 \
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| SCCR_ENCCM_3 \
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| SCCR_USBCM_3 )
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#define SCCR_DEFAULT 0xFFFFFFFF
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#endif /* __MPC83XX_H__ */
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