Fix coding style issues; update CHANGELOG.
Signed-off-by: Wolfgang Denk <wd@denx.de>
This commit is contained in:
@@ -1,7 +1,7 @@
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#
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# Copyright (C) 2007
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# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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#
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#
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# Copyright (C) 2007
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# Kenati Technologies, Inc.
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#
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@@ -29,4 +29,3 @@
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#
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TEXT_BASE = 0x8FFC0000
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@@ -1,7 +1,7 @@
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/*
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* Copyright (C) 2007
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*
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*
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* Copyright (C) 2007
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* Kenati Technologies, Inc.
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*
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@@ -52,19 +52,19 @@ lowlevel_init:
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mov.l r0, @r1
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mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0
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mov.l MSTPCR0_D, r0 !
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mov.l MSTPCR0_D, r0 !
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mov.l r0, @r1
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mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2
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mov.l MSTPCR2_D, r0 !
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mov.l MSTPCR2_D, r0 !
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mov.l r0, @r1
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mov.l SBSCR_A, r1 !
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mov.w SBSCR_D, r0 !
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mov.l SBSCR_A, r1 !
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mov.w SBSCR_D, r0 !
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mov.w r0, @r1
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mov.l PSCR_A, r1 !
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mov.w PSCR_D, r0 !
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mov.l PSCR_A, r1 !
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mov.w PSCR_D, r0 !
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mov.w r0, @r1
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! mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register)
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@@ -80,7 +80,7 @@ lowlevel_init:
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mov.w r0, @r1
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mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register
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mov.l FRQCR_D, r0 !
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mov.l FRQCR_D, r0 !
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mov.l r0, @r1
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mov.l CCR_A, r1 ! Address of Cache Control Register
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@@ -200,11 +200,9 @@ bsc_init:
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rts
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mov #0, r0
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.align 2
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CCR_A: .long CCR
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CCR_A: .long CCR
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MMUCR_A: .long MMUCR
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MSTPCR0_A: .long MSTPCR0
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MSTPCR2_A: .long MSTPCR2
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@@ -223,7 +221,7 @@ FRQCR_D: .long 0x07022538
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PSELA_A: .long 0xa405014E
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PSELA_D: .word 0x0A10
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.align 2
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.align 2
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DRVCR_A: .long 0xa405018A
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DRVCR_D: .word 0x0554
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@@ -4,7 +4,7 @@
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*
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* Copyright (C) 2007
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* Kenati Technologies, Inc.
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*
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*
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* board/ms7722se/ms7722se.c
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*
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* This program is free software; you can redistribute it and/or
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@@ -57,4 +57,3 @@ void led_set_state (unsigned short value)
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{
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*((volatile unsigned short *) LED_BASE) = (value & 0xFF);
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}
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@@ -32,19 +32,19 @@ SECTIONS
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Although size of SDRAM can be either 16 or 32 MBytes,
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we assume 16 MBytes (ie ignore upper half if the full
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32 MBytes is present).
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NOTE: This address must match with the definition of
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TEXT_BASE in config.mk (in this directory).
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*/
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. = 0x8C000000 + (64*1024*1024) - (256*1024);
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PROVIDE (reloc_dst = .);
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PROVIDE (_ftext = .);
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PROVIDE (_fcode = .);
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PROVIDE (_start = .);
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.text :
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{
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cpu/sh4/start.o (.text)
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@@ -89,7 +89,7 @@ SECTIONS
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}
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PROVIDE (__u_boot_cmd_end = .);
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PROVIDE (reloc_dst_end = .);
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PROVIDE (reloc_dst_end = .);
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/* _reloc_dst_end = .; */
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PROVIDE (bss_start = .);
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@@ -103,4 +103,3 @@ SECTIONS
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PROVIDE (_end = .);
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}
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