arc: move common sources in library
"reset.c" and "cpu.c" have no architecture-specific code at all. Others are applicable to either ARC CPU. This change is a preparation to submission of ARCv2 architecture port. Even though ARCv1 and ARCv2 ISAs are not binary compatible most of built-in modules still have the same programming model - AUX registers are mapped in the same addresses and hold the same data (new featues extend existing ones). So only low-level assembly code (start-up, interrupt handlers) is left as CPU(actually ISA)-specific. This significantyl simplifies maintenance of multiple CPUs/ISAs. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
This commit is contained in:
Alexey Brodkin
@@ -4,6 +4,9 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += cache.o
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obj-y += cpu.o
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obj-y += interrupts.o
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obj-y += sections.o
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obj-y += relocate.o
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obj-y += strchr-700.o
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@@ -13,4 +16,7 @@ obj-y += strlen.o
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obj-y += memcmp.o
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obj-y += memcpy-700.o
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obj-y += memset.o
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obj-y += reset.o
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obj-y += timer.o
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obj-$(CONFIG_CMD_BOOTM) += bootm.o
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167
arch/arc/lib/cache.c
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167
arch/arc/lib/cache.c
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@@ -0,0 +1,167 @@
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/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <asm/arcregs.h>
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/* Bit values in IC_CTRL */
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#define IC_CTRL_CACHE_DISABLE (1 << 0)
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/* Bit values in DC_CTRL */
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#define DC_CTRL_CACHE_DISABLE (1 << 0)
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#define DC_CTRL_INV_MODE_FLUSH (1 << 6)
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#define DC_CTRL_FLUSH_STATUS (1 << 8)
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#define CACHE_VER_NUM_MASK 0xF
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int icache_status(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
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return 0;
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return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
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IC_CTRL_CACHE_DISABLE;
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}
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void icache_enable(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
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return;
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write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
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~IC_CTRL_CACHE_DISABLE);
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}
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void icache_disable(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
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return;
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write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
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IC_CTRL_CACHE_DISABLE);
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}
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void invalidate_icache_all(void)
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{
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#ifndef CONFIG_SYS_ICACHE_OFF
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/* Any write to IC_IVIC register triggers invalidation of entire I$ */
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write_aux_reg(ARC_AUX_IC_IVIC, 1);
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#endif /* CONFIG_SYS_ICACHE_OFF */
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}
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int dcache_status(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
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return 0;
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return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
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DC_CTRL_CACHE_DISABLE;
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}
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void dcache_enable(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
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return;
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write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
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~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
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}
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void dcache_disable(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
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return;
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write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
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DC_CTRL_CACHE_DISABLE);
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}
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void flush_dcache_all(void)
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{
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/* If no cache in CPU exit immediately */
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if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
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return;
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/* Do flush of entire cache */
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write_aux_reg(ARC_AUX_DC_FLSH, 1);
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/* Wait flush end */
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while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
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;
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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static void dcache_flush_line(unsigned addr)
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{
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#if (CONFIG_ARC_MMU_VER > 2)
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write_aux_reg(ARC_AUX_DC_PTAG, addr);
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#endif
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write_aux_reg(ARC_AUX_DC_FLDL, addr);
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/* Wait flush end */
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while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
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;
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#ifndef CONFIG_SYS_ICACHE_OFF
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/*
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* Invalidate I$ for addresses range just flushed from D$.
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* If we try to execute data flushed above it will be valid/correct
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*/
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#if (CONFIG_ARC_MMU_VER > 2)
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write_aux_reg(ARC_AUX_IC_PTAG, addr);
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#endif
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write_aux_reg(ARC_AUX_IC_IVIL, addr);
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#endif /* CONFIG_SYS_ICACHE_OFF */
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}
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#endif /* CONFIG_SYS_DCACHE_OFF */
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void flush_dcache_range(unsigned long start, unsigned long end)
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{
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#ifndef CONFIG_SYS_DCACHE_OFF
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unsigned int addr;
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start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
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end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
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for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE)
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dcache_flush_line(addr);
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#endif /* CONFIG_SYS_DCACHE_OFF */
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}
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void invalidate_dcache_range(unsigned long start, unsigned long end)
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{
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#ifndef CONFIG_SYS_DCACHE_OFF
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unsigned int addr;
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start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
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end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
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for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
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#if (CONFIG_ARC_MMU_VER > 2)
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write_aux_reg(ARC_AUX_DC_PTAG, addr);
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#endif
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write_aux_reg(ARC_AUX_DC_IVDL, addr);
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}
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#endif /* CONFIG_SYS_DCACHE_OFF */
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}
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void invalidate_dcache_all(void)
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{
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#ifndef CONFIG_SYS_DCACHE_OFF
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/* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
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write_aux_reg(ARC_AUX_DC_IVDC, 1);
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#endif /* CONFIG_SYS_DCACHE_OFF */
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}
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void flush_cache(unsigned long start, unsigned long size)
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{
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flush_dcache_range(start, start + size);
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}
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47
arch/arc/lib/cpu.c
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47
arch/arc/lib/cpu.c
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@@ -0,0 +1,47 @@
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/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arcregs.h>
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#include <asm/cache.h>
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DECLARE_GLOBAL_DATA_PTR;
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_SYS_ICACHE_OFF
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icache_disable();
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#else
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icache_enable();
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invalidate_icache_all();
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#endif
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flush_dcache_all();
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#ifdef CONFIG_SYS_DCACHE_OFF
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dcache_disable();
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#else
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dcache_enable();
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#endif
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timer_init();
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/* In simulation (ISS) "CHIPID" and "ARCNUM" are all "ff" */
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if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xffffff00) == 0xffffff00)
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gd->arch.running_on_hw = 0;
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else
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gd->arch.running_on_hw = 1;
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gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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int arch_early_init_r(void)
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{
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gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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143
arch/arc/lib/interrupts.c
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143
arch/arc/lib/interrupts.c
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@@ -0,0 +1,143 @@
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/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arcregs.h>
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#include <asm/ptrace.h>
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/* Bit values in STATUS32 */
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#define E1_MASK (1 << 1) /* Level 1 interrupts enable */
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#define E2_MASK (1 << 2) /* Level 2 interrupts enable */
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int interrupt_init(void)
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{
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return 0;
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}
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/*
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* returns true if interrupts had been enabled before we disabled them
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*/
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int disable_interrupts(void)
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{
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int status = read_aux_reg(ARC_AUX_STATUS32);
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int state = (status & (E1_MASK | E2_MASK)) ? 1 : 0;
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status &= ~(E1_MASK | E2_MASK);
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/* STATUS32 register is updated indirectly with "FLAG" instruction */
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__asm__("flag %0" : : "r" (status));
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return state;
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}
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void enable_interrupts(void)
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{
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unsigned int status = read_aux_reg(ARC_AUX_STATUS32);
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status |= E1_MASK | E2_MASK;
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/* STATUS32 register is updated indirectly with "FLAG" instruction */
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__asm__("flag %0" : : "r" (status));
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}
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static void print_reg_file(long *reg_rev, int start_num)
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{
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unsigned int i;
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/* Print 3 registers per line */
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for (i = start_num; i < start_num + 25; i++) {
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printf("r%02u: 0x%08lx\t", i, (unsigned long)*reg_rev);
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if (((i + 1) % 3) == 0)
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printf("\n");
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/* Because pt_regs has registers reversed */
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reg_rev--;
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}
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/* Add new-line if none was inserted in the end of loop above */
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if (((i + 1) % 3) != 0)
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printf("\n");
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}
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void show_regs(struct pt_regs *regs)
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{
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printf("ECR:\t0x%08lx\n", regs->ecr);
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printf("RET:\t0x%08lx\nBLINK:\t0x%08lx\nSTAT32:\t0x%08lx\n",
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regs->ret, regs->blink, regs->status32);
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printf("GP: 0x%08lx\t r25: 0x%08lx\t\n", regs->r26, regs->r25);
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printf("BTA: 0x%08lx\t SP: 0x%08lx\t FP: 0x%08lx\n", regs->bta,
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regs->sp, regs->fp);
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printf("LPS: 0x%08lx\tLPE: 0x%08lx\tLPC: 0x%08lx\n", regs->lp_start,
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regs->lp_end, regs->lp_count);
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print_reg_file(&(regs->r0), 0);
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}
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void bad_mode(struct pt_regs *regs)
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{
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if (regs)
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show_regs(regs);
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panic("Resetting CPU ...\n");
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}
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void do_memory_error(unsigned long address, struct pt_regs *regs)
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{
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printf("Memory error exception @ 0x%lx\n", address);
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bad_mode(regs);
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}
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void do_instruction_error(unsigned long address, struct pt_regs *regs)
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{
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printf("Instruction error exception @ 0x%lx\n", address);
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bad_mode(regs);
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}
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void do_machine_check_fault(unsigned long address, struct pt_regs *regs)
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{
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printf("Machine check exception @ 0x%lx\n", address);
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bad_mode(regs);
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}
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void do_interrupt_handler(void)
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{
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printf("Interrupt fired\n");
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bad_mode(0);
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}
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void do_itlb_miss(struct pt_regs *regs)
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{
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printf("I TLB miss exception\n");
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bad_mode(regs);
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}
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void do_dtlb_miss(struct pt_regs *regs)
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{
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printf("D TLB miss exception\n");
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bad_mode(regs);
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}
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void do_tlb_prot_violation(unsigned long address, struct pt_regs *regs)
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{
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printf("TLB protection violation or misaligned access @ 0x%lx\n",
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address);
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bad_mode(regs);
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}
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void do_privilege_violation(struct pt_regs *regs)
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{
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printf("Privilege violation exception\n");
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bad_mode(regs);
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}
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void do_trap(struct pt_regs *regs)
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{
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printf("Trap exception\n");
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bad_mode(regs);
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}
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void do_extension(struct pt_regs *regs)
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{
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printf("Extension instruction exception\n");
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bad_mode(regs);
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}
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19
arch/arc/lib/reset.c
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19
arch/arc/lib/reset.c
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@@ -0,0 +1,19 @@
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/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <command.h>
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#include <common.h>
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
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{
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printf("Put your restart handler here\n");
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#ifdef DEBUG
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/* Stop debug session here */
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__asm__("brk");
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#endif
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return 0;
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}
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24
arch/arc/lib/timer.c
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24
arch/arc/lib/timer.c
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@@ -0,0 +1,24 @@
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/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/arcregs.h>
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#define NH_MODE (1 << 1) /* Disable timer if CPU is halted */
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int timer_init(void)
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{
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write_aux_reg(ARC_AUX_TIMER0_CTRL, NH_MODE);
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/* Set max value for counter/timer */
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write_aux_reg(ARC_AUX_TIMER0_LIMIT, 0xffffffff);
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/* Set initial count value and restart counter/timer */
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write_aux_reg(ARC_AUX_TIMER0_CNT, 0);
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return 0;
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}
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unsigned long timer_read_counter(void)
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{
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return read_aux_reg(ARC_AUX_TIMER0_CNT);
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}
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