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ARM: tegra: adapt to latest HSP DT binding

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The DT binding for the Tegra186 HSP module apparently wasn't quite final
when I posted initial U-Boot support for it. Add the final DT binding doc
and adapt all code and DT files to match it.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Stephen Warren
2016-07-27 15:24:49 -06:00
committed by Tom Warren
parent e1efe43c71
commit 729c2db7a9
5 changed files with 113 additions and 29 deletions
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47
drivers/mailbox/tegra-hsp.c
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@@ -8,7 +8,19 @@
#include <asm/io.h>
#include <dm.h>
#include <mailbox-uclass.h>
#include <dt-bindings/mailbox/tegra-hsp.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
#define TEGRA_HSP_INT_DIMENSIONING 0x380
#define TEGRA_HSP_INT_DIMENSIONING_NSI_SHIFT 16
#define TEGRA_HSP_INT_DIMENSIONING_NSI_MASK 0xf
#define TEGRA_HSP_INT_DIMENSIONING_NDB_SHIFT 12
#define TEGRA_HSP_INT_DIMENSIONING_NDB_MASK 0xf
#define TEGRA_HSP_INT_DIMENSIONING_NAS_SHIFT 8
#define TEGRA_HSP_INT_DIMENSIONING_NAS_MASK 0xf
#define TEGRA_HSP_INT_DIMENSIONING_NSS_SHIFT 4
#define TEGRA_HSP_INT_DIMENSIONING_NSS_MASK 0xf
#define TEGRA_HSP_INT_DIMENSIONING_NSM_SHIFT 0
#define TEGRA_HSP_INT_DIMENSIONING_NSM_MASK 0xf
#define TEGRA_HSP_DB_REG_TRIGGER 0x0
#define TEGRA_HSP_DB_REG_ENABLE 0x4
@@ -51,7 +63,7 @@ static void tegra_hsp_writel(struct tegra_hsp *thsp, uint32_t val,
static int tegra_hsp_db_id(ulong chan_id)
{
switch (chan_id) {
case TEGRA_HSP_MASTER_BPMP:
case (HSP_MBOX_TYPE_DB << 16) | HSP_DB_MASTER_BPMP:
return TEGRA_HSP_DB_ID_BPMP;
default:
debug("Invalid channel ID\n");
@@ -59,6 +71,21 @@ static int tegra_hsp_db_id(ulong chan_id)
}
}
static int tegra_hsp_of_xlate(struct mbox_chan *chan,
struct fdtdec_phandle_args *args)
{
debug("%s(chan=%p)\n", __func__, chan);
if (args->args_count != 2) {
debug("Invaild args_count: %d\n", args->args_count);
return -EINVAL;
}
chan->id = (args->args[0] << 16) | args->args[1];
return 0;
}
static int tegra_hsp_request(struct mbox_chan *chan)
{
int db_id;
@@ -121,6 +148,7 @@ static int tegra_hsp_bind(struct udevice *dev)
static int tegra_hsp_probe(struct udevice *dev)
{
struct tegra_hsp *thsp = dev_get_priv(dev);
u32 val;
int nr_sm, nr_ss, nr_as;
debug("%s(dev=%p)\n", __func__, dev);
@@ -129,12 +157,14 @@ static int tegra_hsp_probe(struct udevice *dev)
if (thsp->regs == FDT_ADDR_T_NONE)
return -ENODEV;
nr_sm = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-SM",
0);
nr_ss = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-SS",
0);
nr_as = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "nvidia,num-AS",
0);
val = readl(thsp->regs + TEGRA_HSP_INT_DIMENSIONING);
nr_sm = (val >> TEGRA_HSP_INT_DIMENSIONING_NSM_SHIFT) &
TEGRA_HSP_INT_DIMENSIONING_NSM_MASK;
nr_ss = (val >> TEGRA_HSP_INT_DIMENSIONING_NSS_SHIFT) &
TEGRA_HSP_INT_DIMENSIONING_NSS_MASK;
nr_as = (val >> TEGRA_HSP_INT_DIMENSIONING_NAS_SHIFT) &
TEGRA_HSP_INT_DIMENSIONING_NAS_MASK;
thsp->db_base = (1 + (nr_sm >> 1) + nr_ss + nr_as) << 16;
return 0;
@@ -146,6 +176,7 @@ static const struct udevice_id tegra_hsp_ids[] = {
};
struct mbox_ops tegra_hsp_mbox_ops = {
.of_xlate = tegra_hsp_of_xlate,
.request = tegra_hsp_request,
.free = tegra_hsp_free,
.send = tegra_hsp_send,