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blackfin: Set correct early debug serial baudrate.

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Calculate the early uart clock from the system clock registers set by
the bootrom other than the predefine uboot clock macros.

Split the early baudrate setting function and the normal baudrate
setting one.

Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
This commit is contained in:
Sonic Zhang
2013-02-05 19:10:34 +08:00
parent f4d8038439
commit 79f2b3992f
6 changed files with 123 additions and 88 deletions
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43
arch/blackfin/cpu/initcode.c
View File

@@ -194,15 +194,8 @@ static inline void serial_init(void)
#endif
if (BFIN_DEBUG_EARLY_SERIAL) {
int enabled = serial_early_enabled(uart_base);
serial_early_init(uart_base);
/* If the UART is off, that means we need to program
* the baud rate ourselves initially.
*/
if (!enabled)
serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
serial_early_set_baud(uart_base, CONFIG_BAUDRATE);
}
}
@@ -714,37 +707,29 @@ program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
__attribute__((always_inline)) static inline void
update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
{
serial_putc('a');
/* Since we've changed the SCLK above, we may need to update
* the UART divisors (UART baud rates are based on SCLK).
* Do the division by hand as there are no native instructions
* for dividing which means we'd generate a libgcc reference.
*/
if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
unsigned int sdivR, vcoR;
int dividend = sdivB * divB * vcoR;
int divisor = vcoB * sdivR;
unsigned int quotient;
unsigned int sdivR, vcoR;
unsigned int dividend = sdivB * divB * vcoR;
unsigned int divisor = vcoB * sdivR;
unsigned int quotient;
serial_putc('b');
serial_putc('a');
#ifdef __ADSPBF60x__
sdivR = bfin_read_CGU_DIV();
sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f;
sdivR = bfin_read_CGU_DIV();
sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f;
#else
sdivR = bfin_read_PLL_DIV() & 0xf;
vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
sdivR = bfin_read_PLL_DIV() & 0xf;
vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
#endif
for (quotient = 0; dividend > 0; ++quotient)
dividend -= divisor;
serial_early_put_div(quotient - ANOMALY_05000230);
serial_putc('c');
}
serial_putc('d');
quotient = early_division(dividend, divisor);
serial_early_put_div(quotient - ANOMALY_05000230);
serial_putc('c');
}
__attribute__((always_inline)) static inline void