drivers/cpu: Add generic armv8 cpu driver

Add a generic driver that binds to armv8 CPU nodes. The generic driver allows
- to enumerate CPUs present in a system, even when no other driver binds it
- generates ACPI SSDT code for each CPU
- Fill the ACPI MADT table (implemented in a follow up patch)

The newly introduced code could also be reused on other CPU drivers that are
compatible with armv8.

TEST: Booted on QEMU sbsa and verify the driver binds to CPU nodes.
      Confirmed with FWTS that all ACPI processor devices are present.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
This commit is contained in:
Patrick Rudolph
2024-10-23 15:20:01 +02:00
committed by Tom Rini
parent 1289c7ccba
commit 83a2f4a8d2
4 changed files with 102 additions and 0 deletions

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@@ -26,6 +26,12 @@ config CPU_RISCV
help
Support CPU cores for RISC-V architecture.
config CPU_ARMV8
bool "Enable generic ARMv8 CPU driver"
depends on CPU && ARM64
help
Support CPU cores for armv8 architecture.
config CPU_MICROBLAZE
bool "Enable Microblaze CPU driver"
depends on CPU && MICROBLAZE

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@@ -6,10 +6,12 @@
obj-$(CONFIG_CPU) += cpu-uclass.o
obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o
obj-$(CONFIG_ARCH_IMX8) += imx8_cpu.o
obj-$(CONFIG_ARCH_AT91) += at91_cpu.o
obj-$(CONFIG_ARCH_MEDIATEK) += mtk_cpu.o
obj-$(CONFIG_CPU_ARMV8) += armv8_cpu.o
obj-$(CONFIG_CPU_IMX) += imx8_cpu.o
obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o
obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o

73
drivers/cpu/armv8_cpu.c Normal file
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@@ -0,0 +1,73 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2024 9elements GmbH
*/
#include <cpu.h>
#include <dm.h>
#include <acpi/acpigen.h>
#include <asm/armv8/cpu.h>
#include <dm/acpi.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/printk.h>
#include <linux/sizes.h>
static int armv8_cpu_get_desc(const struct udevice *dev, char *buf, int size)
{
int cpuid;
cpuid = (read_midr() & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT;
snprintf(buf, size, "CPU MIDR %04x", cpuid);
return 0;
}
static int armv8_cpu_get_info(const struct udevice *dev,
struct cpu_info *info)
{
info->cpu_freq = 0;
info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
return 0;
}
static int armv8_cpu_get_count(const struct udevice *dev)
{
return uclass_id_count(UCLASS_CPU);
}
#ifdef CONFIG_ACPIGEN
int armv8_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx)
{
uint core_id = dev_seq(dev);
acpigen_write_processor_device(ctx, core_id);
return 0;
}
struct acpi_ops armv8_cpu_acpi_ops = {
.fill_ssdt = armv8_cpu_fill_ssdt,
};
#endif
static const struct cpu_ops cpu_ops = {
.get_count = armv8_cpu_get_count,
.get_desc = armv8_cpu_get_desc,
.get_info = armv8_cpu_get_info,
};
static const struct udevice_id cpu_ids[] = {
{ .compatible = "arm,armv8" },
{}
};
U_BOOT_DRIVER(arm_cpu) = {
.name = "arm-cpu",
.id = UCLASS_CPU,
.of_match = cpu_ids,
.ops = &cpu_ops,
.flags = DM_FLAG_PRE_RELOC,
ACPI_OPS_PTR(&armv8_cpu_acpi_ops)
};

21
drivers/cpu/armv8_cpu.h Normal file
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@@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2024 9elements GmbH
*/
#include <dm/acpi.h>
#include <dm/device.h>
#ifndef _ARMV8_CPU_H_
#define _ARMV8_CPU_H_
/**
* armv8_cpu_fill_ssdt() - Fill the SSDT
* Parses the FDT and writes the SSDT nodes.
*
* @dev: cpu device to generate ACPI tables for
* @ctx: ACPI context pointer
* @return: 0 if OK, or a negative error code.
*/
int armv8_cpu_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx);
#endif