x86: Refactor PIRQ routing support

PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memory-mapped IBASE) to configure the legacy
8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing
support using device tree and move it to a common place, so that we
can easily add PIRQ routing support on a new platform.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

include/dt-bindings/interrupt-router/intel-irq.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _DT_BINDINGS_INTEL_IRQ_H_
+#define _DT_BINDINGS_INTEL_IRQ_H_
+
+/* PCI interrupt pin */
+#define INTA			1
+#define INTB			2
+#define INTC			3
+#define INTD			4
+
+/* PIRQs */
+#define PIRQA			0
+#define PIRQB			1
+#define PIRQC			2
+#define PIRQD			3
+#define PIRQE			4
+#define PIRQF			5
+#define PIRQG			6
+#define PIRQH			7
+
+/* PCI bdf encoding */
+#ifndef PCI_BDF
+#define PCI_BDF(b, d, f)	((b) << 16 | (d) << 11 | (f) << 8)
+#endif
+
+#endif /* _DT_BINDINGS_INTEL_IRQ_H_ */