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mpc86xx: set the DDR BATs after calculating true DDR size

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After determining how much DDR is actually in the system, set DBAT0 and
IBAT0 accordingly.  This ensures that the CPU won't attempt to access
(via speculation) addresses outside of actual memory.

On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB
and kept that way.  If the system has less than 2GB of memory (typical for
an MPC8610 HPCD), the CPU may attempt to access this memory during
speculation.  The zlib code is notorious for generating such memory reads,
and indeed on the MPC8610, uncompressing the Linux kernel causes a machine
check (without this patch).

Currently we are limited to power of two sized DDR since we only use a
single bat.  If a non-power of two size is used that is less than
CONFIG_MAX_MEM_MAPPED u-boot will crash.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Timur Tabi
2010-03-29 12:51:07 -05:00
committed by Kumar Gala
parent 33f57bd553
commit 9ff32d8ccf
8 changed files with 53 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
include/asm-ppc/mmu.h
View File

@@ -213,7 +213,11 @@ extern void print_bats(void);
#define BATL_PADDR(x) ((phys_addr_t)((x & 0xfffe0000) \
| ((x & 0x0e00ULL) << 24) \
| ((x & 0x04ULL) << 30)))
#define BATU_SIZE(x) (1UL << (fls((x & BATU_BL_MAX) >> 2) + 17))
#define BATU_SIZE(x) (1ULL << (fls((x & BATU_BL_MAX) >> 2) + 17))
/* bytes into BATU_BL */
#define TO_BATU_BL(x) \
(u32)((((1ull << __ilog2_u64((u64)x)) / (128 * 1024)) - 1) * 4)
/* Used to set up SDR1 register */
#define HASH_TABLE_SIZE_64K 0x00010000

6
include/configs/MPC8610HPCD.h
View File

@@ -341,10 +341,8 @@
* BAT0 2G Cacheable, non-guarded
* 0x0000_0000 2G DDR
*/
#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
#define CONFIG_SYS_DBAT0L (BATL_PP_RW)
#define CONFIG_SYS_IBAT0L (BATL_PP_RW)
/*
* BAT1 1G Cache-inhibited, guarded

4
include/configs/MPC8641HPCN.h
View File

@@ -482,9 +482,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
* BAT0 DDR
*/
#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
/*
* BAT1 LBC (PIXIS/CF)

2
include/mpc86xx.h
View File

@@ -83,5 +83,7 @@ static __inline__ unsigned long get_l2cr (void)
return l2cr_val;
}
void setup_ddr_bat(phys_addr_t dram_size);
#endif /* _ASMLANGUAGE */
#endif /* __MPC86xx_H__ */