fsl/ddr: updated ddr errata-A008378 for arm and power SoCs
DDR errata-A008378 applies to LS1021-20-22A-R1.0, T1023-R1.0, T1024-R1.0, T1040-42-20-22-R1.0/R1.1, it has been fixed on LS102x Rev2. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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@@ -807,6 +807,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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#define CONFIG_SYS_FSL_SFP_VER_3_0
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#define CONFIG_SYS_FSL_ERRATUM_A008378
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#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
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defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
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@@ -854,6 +855,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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#define CONFIG_SYS_FSL_SFP_VER_3_0
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#define CONFIG_SYS_FSL_ERRATUM_A008378
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#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
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#define CONFIG_E6500
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