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Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

Browse Source 
CI: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/23239

- configs: visionfive2 defconfig: re-enable SPL_SYS_MMCSD_RAW_MODE
- driver: sifive ccache: enable TRUNKCLOCKGATE & REGIONCLOCKGATE
- board: support 64bit Microblaze V
This commit is contained in:
Tom Rini
2024-11-06 10:44:33 -06:00
parent 56accc56b9 d5f5e77818
commit a7a96a37cb
8 changed files with 232 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/riscv/dts/Makefile
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@@ -10,6 +10,7 @@ dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2.dtb
dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb
dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb
dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb
include $(srctree)/scripts/Makefile.dts

99
arch/riscv/dts/xilinx-mbv64.dts Normal file
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@@ -0,0 +1,99 @@
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for AMD MicroBlaze V
*
* (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
/dts-v1/;
#include "binman.dtsi"
/ {
#address-cells = <2>;
#size-cells = <2>;
model = "AMD MicroBlaze V 64bit";
compatible = "qemu,mbv", "amd,mbv";
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <100000000>;
cpu_0: cpu@0 {
compatible = "amd,mbv64", "riscv";
device_type = "cpu";
reg = <0>;
riscv,isa = "rv64imafdc";
i-cache-size = <32768>;
d-cache-size = <32768>;
clock-frequency = <100000000>;
cpu0_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
interrupt-controller;
#interrupt-cells = <1>;
};
};
};
aliases {
serial0 = &uart0;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory@80000000 {
device_type = "memory";
reg = <0 0x80000000 0 0x40000000>;
};
clk100: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
axi: axi {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
bootph-all;
axi_intc: interrupt-controller@41200000 {
compatible = "xlnx,xps-intc-1.00.a";
reg = <0 0x41200000 0 0x1000>;
interrupt-controller;
interrupt-parent = <&cpu0_intc>;
#interrupt-cells = <2>;
kind-of-intr = <0>;
};
xlnx_timer0: timer@41c00000 {
compatible = "xlnx,xps-timer-1.00.a";
reg = <0 0x41c00000 0 0x1000>;
interrupt-parent = <&axi_intc>;
interrupts = <0 2>;
bootph-all;
xlnx,one-timer-only = <0>;
clock-names = "s_axi_aclk";
clocks = <&clk100>;
};
uart0: serial@40600000 {
compatible = "xlnx,xps-uartlite-1.00.a";
reg = <0 0x40600000 0 0x1000>;
interrupt-parent = <&axi_intc>;
interrupts = <1 2>;
bootph-all;
clocks = <&clk100>;
current-speed = <115200>;
xlnx,data-bits = <8>;
xlnx,use-parity = <0>;
};
};
};

2
board/xilinx/Kconfig
View File

@@ -45,7 +45,7 @@ config XILINX_OF_BOARD_DTB_ADDR
default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2
default 0x8000 if MICROBLAZE
default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP
default 0x23000000 if TARGET_XILINX_MBV
default 0x83000000 if TARGET_XILINX_MBV
depends on OF_BOARD || OF_SEPARATE
help
Offset in the memory where the board configuration DTB is placed.

3
configs/starfive_visionfive2_defconfig
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@@ -55,6 +55,9 @@ CONFIG_SPL_PAD_TO=0x0
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x80000000
CONFIG_SPL_SYS_MMCSD_RAW_MODE=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2
CONFIG_SPL_SYS_MALLOC_SIZE=0x400000
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_SPI_FLASH=y

12
configs/xilinx_mbv32_smode_defconfig
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@@ -2,13 +2,13 @@ CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0xe00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x21200000
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv32"
CONFIG_SPL_STACK=0x20200000
CONFIG_SPL_BSS_START_ADDR=0x24000000
CONFIG_SPL_STACK=0x80200000
CONFIG_SPL_BSS_START_ADDR=0x84000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SYS_LOAD_ADDR=0x20200000
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SPL_SIZE_LIMIT=0x40000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x40600000
@@ -16,12 +16,12 @@ CONFIG_DEBUG_UART_CLOCK=1000000
CONFIG_SYS_CLK_FREQ=100000000
CONFIG_BOOT_SCRIPT_OFFSET=0x0
CONFIG_TARGET_XILINX_MBV=y
CONFIG_SPL_OPENSBI_LOAD_ADDR=0x20100000
CONFIG_SPL_OPENSBI_LOAD_ADDR=0x80100000
CONFIG_RISCV_SMODE=y
# CONFIG_SPL_SMP is not set
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x20200000
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y

44
configs/xilinx_mbv64_defconfig Normal file
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@@ -0,0 +1,44 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0xe00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv64"
CONFIG_SPL_STACK=0x80200000
CONFIG_SPL_BSS_START_ADDR=0x84000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SPL_SIZE_LIMIT=0x40000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x40600000
CONFIG_DEBUG_UART_CLOCK=100000000
CONFIG_SYS_CLK_FREQ=100000000
CONFIG_BOOT_SCRIPT_OFFSET=0x0
CONFIG_DEBUG_UART=y
CONFIG_TARGET_XILINX_MBV=y
CONFIG_ARCH_RV64I=y
# CONFIG_SPL_SMP is not set
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_BOARD_LATE_INIT is not set
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
# CONFIG_CMD_MII is not set
CONFIG_CMD_TIMER=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_MTD=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_XILINX_UARTLITE=y
CONFIG_XILINX_TIMER=y
# CONFIG_BINMAN_FDT is not set
CONFIG_PANIC_HANG=y
CONFIG_SPL_GZIP=y

48
configs/xilinx_mbv64_smode_defconfig Normal file
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@@ -0,0 +1,48 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_LEN=0xe00000
CONFIG_NR_DRAM_BANKS=1
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81200000
CONFIG_ENV_SIZE=0x20000
CONFIG_DEFAULT_DEVICE_TREE="xilinx-mbv64"
CONFIG_SPL_STACK=0x80200000
CONFIG_SPL_BSS_START_ADDR=0x84000000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SYS_LOAD_ADDR=0x80200000
CONFIG_SPL_SIZE_LIMIT=0x40000
CONFIG_SPL=y
CONFIG_DEBUG_UART_BASE=0x40600000
CONFIG_DEBUG_UART_CLOCK=1000000
CONFIG_SYS_CLK_FREQ=100000000
CONFIG_BOOT_SCRIPT_OFFSET=0x0
CONFIG_TARGET_XILINX_MBV=y
CONFIG_SPL_OPENSBI_LOAD_ADDR=0x80100000
CONFIG_ARCH_RV64I=y
CONFIG_RISCV_SMODE=y
# CONFIG_SPL_SMP is not set
CONFIG_REMAKE_ELF=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
# CONFIG_BOARD_LATE_INIT is not set
CONFIG_SPL_MAX_SIZE=0x40000
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS=0x2
# CONFIG_CMD_MII is not set
CONFIG_CMD_TIMER=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DM_MTD=y
CONFIG_DEBUG_UART_UARTLITE=y
CONFIG_DEBUG_UART_ANNOUNCE=y
CONFIG_DEBUG_UART_SKIP_INIT=y
CONFIG_XILINX_UARTLITE=y
# CONFIG_RISCV_TIMER is not set
CONFIG_XILINX_TIMER=y
# CONFIG_BINMAN_FDT is not set
CONFIG_PANIC_HANG=y
CONFIG_SPL_GZIP=y

33
drivers/cache/cache-sifive-ccache.c vendored
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@@ -14,8 +14,17 @@
#define SIFIVE_CCACHE_WAY_ENABLE 0x008
#define SIFIVE_CCACHE_TRUNKCLOCKGATE 0x1000
#define SIFIVE_CCACHE_TRUNKCLOCKGATE_DISABLE BIT(0)
#define SIFIVE_CCACHE_REGIONCLOCKGATE_DISABLE BIT(1)
struct sifive_ccache {
void __iomem *base;
bool has_cg;
};
struct sifive_ccache_quirks {
bool has_cg;
};
static int sifive_ccache_enable(struct udevice *dev)
@@ -30,6 +39,14 @@ static int sifive_ccache_enable(struct udevice *dev)
writel(ways - 1, priv->base + SIFIVE_CCACHE_WAY_ENABLE);
if (priv->has_cg) {
/* enable clock gating bits */
config = readl(priv->base + SIFIVE_CCACHE_TRUNKCLOCKGATE);
config &= ~(SIFIVE_CCACHE_TRUNKCLOCKGATE_DISABLE |
SIFIVE_CCACHE_REGIONCLOCKGATE_DISABLE);
writel(config, priv->base + SIFIVE_CCACHE_TRUNKCLOCKGATE);
}
return 0;
}
@@ -50,7 +67,9 @@ static const struct cache_ops sifive_ccache_ops = {
static int sifive_ccache_probe(struct udevice *dev)
{
struct sifive_ccache *priv = dev_get_priv(dev);
const struct sifive_ccache_quirks *quirk = (void *)dev_get_driver_data(dev);
priv->has_cg = quirk->has_cg;
priv->base = dev_read_addr_ptr(dev);
if (!priv->base)
return -EINVAL;
@@ -58,10 +77,18 @@ static int sifive_ccache_probe(struct udevice *dev)
return 0;
}
static const struct sifive_ccache_quirks fu540_ccache = {
.has_cg = false,
};
static const struct sifive_ccache_quirks ccache0 = {
.has_cg = true,
};
static const struct udevice_id sifive_ccache_ids[] = {
{ .compatible = "sifive,fu540-c000-ccache" },
{ .compatible = "sifive,fu740-c000-ccache" },
{ .compatible = "sifive,ccache0" },
{ .compatible = "sifive,fu540-c000-ccache", .data = (ulong)&fu540_ccache },
{ .compatible = "sifive,fu740-c000-ccache", .data = (ulong)&fu540_ccache },
{ .compatible = "sifive,ccache0", .data = (ulong)&ccache0 },
{}
};