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Makefile.host.tmp: add a new script to refactor tools

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This commit adds scripts/Makefile.host.tmp which will
be used in the next commit to convert makefiles
under tools/ directory to Kbuild style.

Notice this script, scripts/Makefile.host.tmp
is temporary.

When switching over to real Kbuild,
it will be replaced with scripts/Makefile.host of Linux Kernel.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
This commit is contained in:
Masahiro Yamada
2014-02-04 17:24:09 +09:00
committed by Tom Rini
parent ea531e3afd
commit ad71fa9971
2 changed files with 75 additions and 3 deletions
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17
scripts/Makefile.build
View File

@@ -7,15 +7,23 @@ include $(TOPDIR)/config.mk
LIB := $(obj)built-in.o
LIBGCC = $(obj)libgcc.o
SRCS :=
subdir-y :=
obj-dirs :=
include Makefile
# Do not include host rules unless needed
ifneq ($(hostprogs-y)$(hostprogs-m),)
include $(SRCTREE)/scripts/Makefile.host.tmp
endif
# Going forward use the following
obj-y := $(sort $(obj-y))
extra-y := $(sort $(extra-y))
always := $(sort $(always))
lib-y := $(sort $(lib-y))
subdir-y := $(patsubst %/,%,$(filter %/, $(obj-y)))
subdir-y += $(patsubst %/,%,$(filter %/, $(obj-y)))
obj-y := $(patsubst %/, %/built-in.o, $(obj-y))
subdir-obj-y := $(filter %/built-in.o, $(obj-y))
subdir-obj-y := $(addprefix $(obj),$(subdir-obj-y))
@@ -25,7 +33,8 @@ SRCS += $(wildcard $(obj-y:.o=.c) $(obj-y:.o=.S) $(lib-y:.o=.c) \
OBJS := $(addprefix $(obj),$(obj-y))
# $(obj-dirs) is a list of directories that contain object files
obj-dirs := $(dir $(OBJS))
obj-dirs += $(dir $(OBJS))
# Create directories for object files if directory does not exist
# Needed when obj-y := dir/file.o syntax is used
@@ -33,7 +42,7 @@ _dummy := $(foreach d,$(obj-dirs), $(shell [ -d $(d) ] || mkdir -p $(d)))
LGOBJS := $(addprefix $(obj),$(sort $(lib-y)))
all: $(LIB) $(addprefix $(obj),$(extra-y))
all: $(LIB) $(addprefix $(obj),$(extra-y) $(always)) $(subdir-y)
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
@@ -48,7 +57,9 @@ endif
ifneq ($(subdir-obj-y),)
# Descending
$(subdir-obj-y): $(subdir-y)
endif
ifneq ($(subdir-y),)
$(subdir-y): FORCE
$(MAKE) -C $@ -f $(TOPDIR)/scripts/Makefile.build
endif