keymile: Fix Coding style issues for keymile boards.
- use I/O accessors
-> For accessing the FPGA therefore a struct km_bec_fpga
is introduced.
- no longer externs needed
- to defines, that only select functions, don;t assign a
numeric value
- Codingstyle changes to prevent checkpatch errors/warnings
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
cc: Kim Phillips <kim.phillips@freescale.com>
cc: Holger Brunck <holger.brunck@keymile.com>
cc: Wolfgang Denk <wd@denx.de>
cc: Detlev Zundel <dzu@denx.de>
cc: Valentin Longchamp <valentin.longchamp@keymile.com>
cc: Prafulla Wadaskar <prafulla@marvell.com>
This commit is contained in:
Heiko Schocher
committed by
Wolfgang Denk
Wolfgang Denk
parent
802d996324
commit
b11f53f31b
@@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2008
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* (C) Copyright 2008-2011
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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@@ -25,7 +25,7 @@
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#define __CONFIG_KEYMILE_H
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/* Do boardspecific init for all boards */
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#define CONFIG_BOARD_EARLY_INIT_R 1
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#define CONFIG_BOARD_EARLY_INIT_R
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#define CONFIG_BOOTCOUNT_LIMIT
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@@ -63,44 +63,44 @@
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#define CONFIG_JFFS2_CMDLINE
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#define CONFIG_CMD_MTDPARTS
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#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
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#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_HUSH_INIT_VAR 1
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#define CONFIG_HUSH_INIT_VAR
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#define CONFIG_SYS_ALT_MEMTEST /* memory test, takes time */
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#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CONFIG_SYS_MEMTEST_START 0x00100000
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#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
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#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
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#define CONFIG_SYS_LOAD_ADDR 0x100000
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#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CONFIG_SYS_HZ 1000 /* decr. freq: 1 ms ticks */
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_LOADS_ECHO
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#define CONFIG_SYS_LOADS_BAUD_CHANGE
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#define CONFIG_SYS_BOARD_DRAM_INIT /* Used board specific dram_init */
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/*
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@@ -108,28 +108,28 @@
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* to modify in a centralized location. This is used in the HDLC
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* driver to set the MAC.
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*/
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#define CONFIG_CHECK_ETHERNET_PRESENT 1
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#define CONFIG_CHECK_ETHERNET_PRESENT
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#define CONFIG_SYS_SLOT_ID_BASE CONFIG_SYS_PIGGY_BASE
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#define CONFIG_SYS_SLOT_ID_OFF (0x07) /* register offset */
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#define CONFIG_SYS_SLOT_ID_MASK (0x3f) /* mask for slot ID bits */
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#define CONFIG_I2C_MULTI_BUS 1
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#define CONFIG_I2C_MULTI_BUS
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#define CONFIG_SYS_MAX_I2C_BUS 1
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#define CONFIG_SYS_I2C_INIT_BOARD 1
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#define CONFIG_I2C_MUX 1
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#define CONFIG_SYS_I2C_INIT_BOARD
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#define CONFIG_I2C_MUX
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/* EEprom support */
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#define CONFIG_SYS_I2C_MULTI_EEPROMS 1
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#define CONFIG_SYS_I2C_MULTI_EEPROMS
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
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/* Support the IVM EEprom */
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#define CONFIG_SYS_IVM_EEPROM_ADR 0x50
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#define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400
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#define CONFIG_SYS_IVM_EEPROM_PAGE_LEN 0x100
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#define CONFIG_SYS_FLASH_PROTECTION 1
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#define CONFIG_SYS_FLASH_PROTECTION
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/*
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* BOOTP options
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@@ -141,7 +141,7 @@
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#define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */
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#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
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#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
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/* UBI Support for all Keymile boards */
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#define CONFIG_CMD_UBI
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@@ -6,6 +6,9 @@
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* (C) Copyright 2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2010-2011
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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@@ -25,7 +28,10 @@
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* MA 02110-1301 USA
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*/
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/* for linking errors see http://lists.denx.de/pipermail/u-boot/2009-July/057350.html */
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/*
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* for linking errors see
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* http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
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*/
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#ifndef _CONFIG_KM_ARM_H
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#define _CONFIG_KM_ARM_H
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@@ -23,11 +23,9 @@
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 family */
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#define CONFIG_QE 1 /* Has QE */
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#define CONFIG_MPC83xx 1 /* MPC83xx family */
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#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
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#define CONFIG_KMETER1 1 /* KMETER1 board specific */
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#define CONFIG_QE /* Has QE */
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#define CONFIG_MPC8360 /* MPC8360 CPU specific */
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#define CONFIG_KMETER1 /* KMETER1 board specific */
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#define CONFIG_HOSTNAME kmeter1
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#define CONFIG_SYS_TEXT_BASE 0xF0000000
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@@ -42,7 +40,7 @@
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"mtdparts=boot:768k(u-boot),128k(env),128k(envred)," \
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"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
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#define CONFIG_MISC_INIT_R 1
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#define CONFIG_MISC_INIT_R
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/*
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* System Clock Setup
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*/
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@@ -114,8 +112,9 @@
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#define CONFIG_SYS_DDR_SIZE 2048 /* MB */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
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CSCONFIG_ROW_BIT_13 | \
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CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
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CSCONFIG_ROW_BIT_13 | \
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CSCONFIG_COL_BIT_10 | \
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CSCONFIG_ODT_WR_ACS)
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#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
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SDRAM_CFG_SREN)
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@@ -137,14 +136,14 @@
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(0 << TIMING_CFG0_WRT_SHIFT) | \
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(0 << TIMING_CFG0_RWT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_1 (( TIMING_CFG1_CASLAT_50) | \
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( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
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( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
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( 3 << TIMING_CFG1_WRREC_SHIFT) | \
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( 7 << TIMING_CFG1_REFREC_SHIFT) | \
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( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
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( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
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( 3 << TIMING_CFG1_PRETOACT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
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(2 << TIMING_CFG1_WRTORD_SHIFT) | \
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(2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
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(3 << TIMING_CFG1_WRREC_SHIFT) | \
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(7 << TIMING_CFG1_REFREC_SHIFT) | \
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(3 << TIMING_CFG1_ACTTORW_SHIFT) | \
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(8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
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(3 << TIMING_CFG1_PRETOACT_SHIFT))
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#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
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(3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
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@@ -172,7 +171,7 @@
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#undef CONFIG_SYS_RAMBOOT
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#endif
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
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#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve for Mon */
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/*
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* Initial RAM Base Address Setup
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@@ -180,7 +179,8 @@
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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@@ -208,7 +208,7 @@
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#define CONFIG_SYS_FLASH_PROTECTION 1
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
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#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */
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#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
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@@ -220,8 +220,9 @@
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OR_GPCM_SCY_5 | \
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OR_GPCM_TRLX | OR_GPCM_EAD)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
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/* max num of sects on one chip */
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#define CONFIG_SYS_MAX_FLASH_SECT 512
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#undef CONFIG_SYS_FLASH_CHECKSUM
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@@ -229,13 +230,13 @@
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/*
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* PRIO1/PIGGY on the local bus CS1
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*/
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#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
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#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_PIGGY_BASE
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#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */
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#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_PIGGY_BASE | \
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(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
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BR_V)
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#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \
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#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | \
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OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
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OR_GPCM_SCY_2 | \
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OR_GPCM_TRLX | OR_GPCM_EAD)
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@@ -243,7 +244,7 @@
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/*
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* PAXE on the local bus CS3
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*/
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#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE /* Window base at flash base */
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#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
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#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
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#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \
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@@ -267,8 +268,8 @@
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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/* Pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define CONFIG_OF_LIBFDT
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#define CONFIG_OF_BOARD_SETUP
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#define CONFIG_OF_STDOUT_VIA_ALIAS
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/*
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@@ -278,7 +279,7 @@
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#undef CONFIG_PCI /* No PCI */
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#ifndef CONFIG_NET_MULTI
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#define CONFIG_NET_MULTI 1
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#define CONFIG_NET_MULTI
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#endif
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/*
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* QE UEC ethernet configuration
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@@ -291,7 +292,7 @@
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#ifdef CONFIG_UEC_ETH1
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#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */
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#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */
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#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII */
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#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17
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#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
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#define CONFIG_SYS_UEC1_PHY_ADDR 0
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@@ -305,17 +306,19 @@
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#ifndef CONFIG_SYS_RAMBOOT
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
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#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN)
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
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CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#else /* CFG_RAMBOOT */
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#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
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#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
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#define CONFIG_SYS_NO_FLASH /* Flash is not usable now */
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#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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#define CONFIG_ENV_SIZE 0x2000
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#endif /* CFG_RAMBOOT */
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@@ -333,9 +336,9 @@
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/* EEprom support */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
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/* I2C SYSMON (LM75, AD7414 is almost compatible) */
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#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
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#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
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/* I2C SYSMON (LM75, AD7414 is almost compatible) */
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#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
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#define CONFIG_DTT_SENSORS {0, 1, 2, 3} /* Sensor addresses */
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#define CONFIG_SYS_DTT_MAX_TEMP 70
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#define CONFIG_SYS_DTT_LOW_TEMP -30
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#define CONFIG_SYS_DTT_HYSTERESIS 3
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@@ -361,7 +364,7 @@
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* have to be in the first 256 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
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/*
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* Core HID Setup
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@@ -375,45 +378,54 @@
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* MMU Setup
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*/
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#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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#define CONFIG_HIGH_BATS /* High BATs supported */
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/* DDR: cache cacheable */
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#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
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BATU_VS | BATU_VP)
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#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
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#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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/* IMMRBAR & PCI IO: cache-inhibit and guarded */
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#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
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BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
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#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | \
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BATU_VP)
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#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
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#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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|
||||
/* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */
|
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
|
||||
BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
|
||||
|
||||
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
|
||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
|
||||
BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
|
||||
|
||||
/* Stack in dcache: cacheable, no memory coherence */
|
||||
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
|
||||
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
|
||||
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
|
||||
|
||||
/* PAXE: icache cacheable, but dcache-inhibit and guarded */
|
||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
|
||||
BATL_MEMCOHERENCE)
|
||||
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \
|
||||
BATU_VS | BATU_VP)
|
||||
#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
|
||||
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
||||
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
|
||||
|
||||
@@ -29,15 +29,12 @@
|
||||
* (easy to change)
|
||||
*/
|
||||
|
||||
#define CONFIG_MPC8247 1
|
||||
#define CONFIG_MPC8272_FAMILY 1
|
||||
#define CONFIG_MGCOGE 1
|
||||
#define CONFIG_MPC8247
|
||||
#define CONFIG_MGCOGE
|
||||
#define CONFIG_HOSTNAME mgcoge
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFE000000
|
||||
|
||||
#define CONFIG_CPM2 1 /* Has a CPM2 */
|
||||
|
||||
/* include common defines/options for all Keymile boards */
|
||||
#include "keymile-common.h"
|
||||
|
||||
@@ -69,13 +66,13 @@
|
||||
#define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
|
||||
#undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
|
||||
#undef CONFIG_ETHER_NONE /* No external Ethernet */
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#define CONFIG_NET_MULTI
|
||||
|
||||
#define CONFIG_ETHER_INDEX 4
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_SYS_SCC_TOUT_LOOP 10000000
|
||||
|
||||
# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
|
||||
# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
|
||||
|
||||
#ifndef CONFIG_8260_CLKIN
|
||||
#define CONFIG_8260_CLKIN 66000000 /* in Hz */
|
||||
@@ -113,8 +110,9 @@
|
||||
#define CONFIG_SYS_FLASH_SIZE 32
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 3 /* max num of flash banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 3
|
||||
/* max num of sects on one chip */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 512
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE_1 0x50000000
|
||||
#define CONFIG_SYS_FLASH_SIZE_1 32
|
||||
@@ -130,24 +128,26 @@
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384KB for Monitor */
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 << 10)
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
|
||||
#ifdef CONFIG_ENV_IS_IN_FLASH
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
|
||||
CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
|
||||
CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
#endif /* CONFIG_ENV_IS_IN_FLASH */
|
||||
#define CONFIG_ENV_BUFFER_PRINT 1
|
||||
#define CONFIG_ENV_BUFFER_PRINT
|
||||
|
||||
/* enable I2C and select the hardware/software driver */
|
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
|
||||
#define CONFIG_SOFT_I2C /* I2C bit-banged */
|
||||
#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
|
||||
@@ -159,15 +159,23 @@
|
||||
#define I2C_ACTIVE (iop->pdir |= 0x00010000)
|
||||
#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
|
||||
#define I2C_READ ((iop->pdat & 0x00010000) != 0)
|
||||
#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
|
||||
else iop->pdat &= ~0x00010000
|
||||
#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
|
||||
else iop->pdat &= ~0x00020000
|
||||
#define I2C_SDA(bit) do { \
|
||||
if (bit) \
|
||||
iop->pdat |= 0x00010000; \
|
||||
else \
|
||||
iop->pdat &= ~0x00010000; \
|
||||
} while (0)
|
||||
#define I2C_SCL(bit) do { \
|
||||
if (bit) \
|
||||
iop->pdat |= 0x00020000; \
|
||||
else \
|
||||
iop->pdat &= ~0x00020000; \
|
||||
} while (0)
|
||||
#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
|
||||
|
||||
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
|
||||
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
|
||||
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
|
||||
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
|
||||
#define CONFIG_DTT_LM75 /* ON Semi's LM75 */
|
||||
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
|
||||
#define CONFIG_SYS_DTT_MAX_TEMP 70
|
||||
#define CONFIG_SYS_DTT_LOW_TEMP -30
|
||||
#define CONFIG_SYS_DTT_HYSTERESIS 3
|
||||
@@ -178,8 +186,9 @@
|
||||
#define CONFIG_SYS_IMMR 0xF0000000
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/* Hard reset configuration word */
|
||||
@@ -194,11 +203,11 @@
|
||||
#define CONFIG_SYS_HRCW_SLAVE6 0
|
||||
#define CONFIG_SYS_HRCW_SLAVE7 0
|
||||
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
|
||||
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_HID0_INIT 0
|
||||
@@ -211,14 +220,16 @@
|
||||
#define CONFIG_SYS_BCR 0x10000000
|
||||
#define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
*-----------------------------------------------------------------------
|
||||
* RMR - Reset Mode Register 5-5
|
||||
*-----------------------------------------------------------------------
|
||||
* turn on Checkstop Reset Enable
|
||||
*/
|
||||
#define CONFIG_SYS_RMR 0
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
*-----------------------------------------------------------------------
|
||||
* TMCNTSC - Time Counter Status and Control 4-40
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
|
||||
@@ -226,7 +237,8 @@
|
||||
*/
|
||||
#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 4-42
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
|
||||
@@ -234,7 +246,8 @@
|
||||
*/
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
/*
|
||||
*-----------------------------------------------------------------------
|
||||
* RCCR - RISC Controller Configuration 13-7
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
@@ -265,14 +278,16 @@
|
||||
ORxG_TRLX )
|
||||
|
||||
|
||||
/* Bank 1 - 60x bus SDRAM
|
||||
/*
|
||||
* Bank 1 - 60x bus SDRAM
|
||||
*/
|
||||
#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
|
||||
#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
|
||||
#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20)
|
||||
|
||||
#define CONFIG_SYS_MPTPR 0x1800
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
/*
|
||||
*-----------------------------------------------------------------------------
|
||||
* Address for Mode Register Set (MRS) command
|
||||
*-----------------------------------------------------------------------------
|
||||
*/
|
||||
@@ -286,8 +301,9 @@
|
||||
|
||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1
|
||||
|
||||
/* SDRAM initialization values
|
||||
*/
|
||||
/*
|
||||
* SDRAM initialization values
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
|
||||
ORxS_BPD_8 |\
|
||||
@@ -304,8 +320,9 @@
|
||||
PSDMR_WRC_1C |\
|
||||
PSDMR_CL_2)
|
||||
|
||||
/* GPIO/PIGGY on CS3 initialization values
|
||||
*/
|
||||
/*
|
||||
* GPIO/PIGGY on CS3 initialization values
|
||||
*/
|
||||
#define CONFIG_SYS_PIGGY_BASE 0x30000000
|
||||
#define CONFIG_SYS_PIGGY_SIZE 128
|
||||
|
||||
@@ -316,8 +333,9 @@
|
||||
ORxG_CSNT | ORxG_ACS_DIV2 |\
|
||||
ORxG_SCY_3_CLK | ORxG_TRLX )
|
||||
|
||||
/* Board FPGA on CS4 initialization values
|
||||
*/
|
||||
/*
|
||||
* Board FPGA on CS4 initialization values
|
||||
*/
|
||||
#define CONFIG_SYS_FPGA_BASE 0x40000000
|
||||
#define CONFIG_SYS_FPGA_SIZE 1 /*1KB*/
|
||||
|
||||
@@ -328,8 +346,9 @@
|
||||
ORxG_CSNT | ORxG_ACS_DIV2 |\
|
||||
ORxG_SCY_3_CLK | ORxG_TRLX )
|
||||
|
||||
/* CFG-Flash on CS5 initialization values
|
||||
*/
|
||||
/*
|
||||
* CFG-Flash on CS5 initialization values
|
||||
*/
|
||||
#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
|
||||
BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
|
||||
|
||||
@@ -338,12 +357,12 @@
|
||||
ORxG_CSNT | ORxG_ACS_DIV2 |\
|
||||
ORxG_SCY_5_CLK | ORxG_TRLX )
|
||||
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
|
||||
#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_FIT 1
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
#define CONFIG_FIT
|
||||
#define CONFIG_OF_LIBFDT
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
|
||||
#define OF_TBCLK (bd->bi_busfreq / 4)
|
||||
#define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
|
||||
|
||||
Reference in New Issue
Block a user