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arm: dts: mt7629: fix sgmii clock selection for ethernet

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Setup correct parent of clock CLK_TOP_SGMII_REF_1_SEL to allow
sgmiisys1 work correctly.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
This commit is contained in:
Weijie Gao
2024-12-17 16:39:20 +08:00
committed by Tom Rini
parent 6e45549f4d
commit ba365c3d23
1 changed files with 3 additions and 1 deletions
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4
arch/arm/dts/mt7629.dtsi
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@@ -314,8 +314,10 @@
"sgmii2_cdr_ref", "sgmii2_cdr_fb",
"sgmii_ck", "eth2pll";
assigned-clocks = <&topckgen CLK_TOP_ETH_SEL>,
<&topckgen CLK_TOP_F10M_REF_SEL>;
<&topckgen CLK_TOP_F10M_REF_SEL>,
<&topckgen CLK_TOP_SGMII_REF_1_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>,
<&topckgen CLK_TOP_SYSPLL4_D16>,
<&topckgen CLK_TOP_SGMIIPLL_D2>;
power-domains = <&scpsys MT7629_POWER_DOMAIN_ETHSYS>;
resets = <&ethsys ETHSYS_FE_RST>;