XPedite5370 board support
Initial support for Extreme Engineering Solutions XPedite5370 - a MPC8572-based 3U VPX single board computer with a PMC/XMC site. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
This commit is contained in:
Peter Tyser
committed by
Andrew Fleming-AFLEMING
Andrew Fleming-AFLEMING
parent
e92739d34e
commit
ccf0fdd02b
56
board/xes/common/Makefile
Normal file
56
board/xes/common/Makefile
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@@ -0,0 +1,56 @@
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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ifneq ($(OBJTREE),$(SRCTREE))
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$(shell mkdir -p $(obj)board/$(VENDOR)/common)
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endif
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LIB = $(obj)lib$(VENDOR).a
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COBJS-$(CONFIG_MPC8572) += fsl_8572_clk.o
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COBJS-$(CONFIG_MPC85xx) += fsl_85xx_ddr.o
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COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_85xx_pci.o
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SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS-y))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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#########################################################################
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# defines $(obj).depend target
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include $(SRCTREE)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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51
board/xes/common/fsl_8572_clk.c
Normal file
51
board/xes/common/fsl_8572_clk.c
Normal file
@@ -0,0 +1,51 @@
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/*
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* Copyright 2008 Extreme Engineering Solutions, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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/*
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* Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
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*/
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unsigned long get_board_sys_clk(ulong dummy)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 gpporcr = gur->gpporcr;
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if (gpporcr & 0x10000)
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return 66666666;
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else
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return 50000000;
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}
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/*
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* Return DDR input clock - synchronous with SYSCLK or 66 MHz
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*/
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unsigned long get_board_ddr_clk(ulong dummy)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
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if (ddr_ratio == 0x7)
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return get_board_sys_clk(dummy);
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return 66666666;
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}
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93
board/xes/common/fsl_85xx_ddr.c
Normal file
93
board/xes/common/fsl_85xx_ddr.c
Normal file
@@ -0,0 +1,93 @@
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/*
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* Copyright 2008 Extreme Engineering Solutions, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/mmu.h>
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size = fsl_ddr_sdram();
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/* Initialize and enable DDR ECC */
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ddr_enable_ecc(dram_size);
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#endif
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return dram_size;
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}
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#if defined(CONFIG_DDR_ECC) || (CONFIG_NUM_DDR_CONTROLLERS > 1)
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void board_add_ram_info(int use_default)
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{
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#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
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volatile ccsr_ddr_t *ddr1 = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
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#endif
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puts(" (");
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#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
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/* Print interleaving information */
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if (ddr1->cs0_config & 0x20000000) {
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switch ((ddr1->cs0_config >> 24) & 0xf) {
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case 0:
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puts("cache line");
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break;
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case 1:
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puts("page");
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break;
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case 2:
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puts("bank");
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break;
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case 3:
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puts("super-bank");
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break;
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default:
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puts("invalid");
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break;
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}
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} else {
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puts("no");
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}
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puts(" interleaving");
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#endif
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#if (CONFIG_NUM_DDR_CONTROLLERS > 1) && defined(CONFIG_DDR_ECC)
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puts(", ");
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#endif
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#if defined(CONFIG_DDR_ECC)
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puts("ECC enabled");
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#endif
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puts(")");
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}
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#endif /* CONFIG_DDR_ECC || CONFIG_NUM_DDR_CONTROLLERS > 1 */
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265
board/xes/common/fsl_85xx_pci.c
Normal file
265
board/xes/common/fsl_85xx_pci.c
Normal file
@@ -0,0 +1,265 @@
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/*
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* Copyright 2008 Extreme Engineering Solutions, Inc.
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* Copyright 2007-2008 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/immap_85xx.h>
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#include <asm/immap_fsl_pci.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
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extern void fsl_pci_init(struct pci_controller *hose);
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int first_free_busno = 0;
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif
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#ifdef CONFIG_PCIE2
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static struct pci_controller pcie2_hose;
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#endif
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#ifdef CONFIG_PCIE3
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static struct pci_controller pcie3_hose;
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#endif
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/* Correlate host/agent POR bits to usable info. Table 4-14 */
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struct host_agent_cfg_t {
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uchar pcie_root[3];
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uchar rio_host;
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} host_agent_cfg[8] = {
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{{0, 0, 0}, 0},
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{{0, 1, 1}, 1},
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{{1, 0, 1}, 0},
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{{1, 1, 0}, 1},
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{{0, 0, 1}, 0},
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{{0, 1, 0}, 1},
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{{1, 0, 0}, 0},
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{{1, 1, 1}, 1}
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};
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/* Correlate port width POR bits to usable info. Table 4-15 */
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struct io_port_cfg_t {
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uchar pcie_width[3];
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uchar rio_width;
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} io_port_cfg[16] = {
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 0},
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{{4, 0, 0}, 0},
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{{4, 4, 0}, 0},
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 4},
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{{4, 2, 2}, 0},
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 0},
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{{0, 0, 0}, 0},
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{{4, 0, 0}, 4},
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{{4, 0, 0}, 4},
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{{0, 0, 0}, 4},
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{{0, 0, 0}, 4},
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{{8, 0, 0}, 0},
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};
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void pci_init_board(void)
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{
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struct pci_controller *hose;
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volatile ccsr_fsl_pci_t *pci;
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int width;
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int host;
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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uint devdisr = gur->devdisr;
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uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
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struct pci_region *r;
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debug(" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
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devdisr, io_sel, host_agent);
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#ifdef CONFIG_PCIE1
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pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
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hose = &pcie1_hose;
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host = host_agent_cfg[host_agent].pcie_root[0];
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width = io_port_cfg[io_sel].pcie_width[0];
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r = hose->regions;
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if (width && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
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printf("\n PCIE1 connected as %s (x%d)",
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host ? "Root Complex" : "End Point", width);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug(" with errors. Clearing. Now 0x%08x",
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pci->pme_msg_det);
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}
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printf("\n");
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/* inbound */
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r += fsl_pci_setup_inbound_windows(r);
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/* outbound memory */
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_MEM_BASE,
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CONFIG_SYS_PCIE1_MEM_PHYS,
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CONFIG_SYS_PCIE1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(r++,
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CONFIG_SYS_PCIE1_IO_BASE,
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CONFIG_SYS_PCIE1_IO_PHYS,
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CONFIG_SYS_PCIE1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = r - hose->regions;
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hose->first_busno = first_free_busno;
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pci_setup_indirect(hose, (int)&pci->cfg_addr,
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(int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno = hose->last_busno+1;
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printf(" PCIE1 on bus %02x - %02x\n",
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hose->first_busno, hose->last_busno);
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
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#endif /* CONFIG_PCIE1 */
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#ifdef CONFIG_PCIE2
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pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
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hose = &pcie2_hose;
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host = host_agent_cfg[host_agent].pcie_root[1];
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width = io_port_cfg[io_sel].pcie_width[1];
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r = hose->regions;
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|
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if (width && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
|
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printf("\n PCIE2 connected as %s (x%d)",
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host ? "Root Complex" : "End Point", width);
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if (pci->pme_msg_det) {
|
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pci->pme_msg_det = 0xffffffff;
|
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debug(" with errors. Clearing. Now 0x%08x",
|
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pci->pme_msg_det);
|
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}
|
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printf("\n");
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/* inbound */
|
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r += fsl_pci_setup_inbound_windows(r);
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|
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/* outbound memory */
|
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pci_set_region(r++,
|
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CONFIG_SYS_PCIE2_MEM_BASE,
|
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CONFIG_SYS_PCIE2_MEM_PHYS,
|
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CONFIG_SYS_PCIE2_MEM_SIZE,
|
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PCI_REGION_MEM);
|
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|
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/* outbound io */
|
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pci_set_region(r++,
|
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CONFIG_SYS_PCIE2_IO_BASE,
|
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CONFIG_SYS_PCIE2_IO_PHYS,
|
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CONFIG_SYS_PCIE2_IO_SIZE,
|
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PCI_REGION_IO);
|
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|
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hose->region_count = r - hose->regions;
|
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|
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hose->first_busno = first_free_busno;
|
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pci_setup_indirect(hose, (int)&pci->cfg_addr,
|
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(int)&pci->cfg_data);
|
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|
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fsl_pci_init(hose);
|
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first_free_busno = hose->last_busno+1;
|
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printf(" PCIE2 on bus %02x - %02x\n",
|
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hose->first_busno, hose->last_busno);
|
||||
|
||||
}
|
||||
#else
|
||||
gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
|
||||
#endif /* CONFIG_PCIE2 */
|
||||
|
||||
#ifdef CONFIG_PCIE3
|
||||
pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
|
||||
hose = &pcie3_hose;
|
||||
host = host_agent_cfg[host_agent].pcie_root[2];
|
||||
width = io_port_cfg[io_sel].pcie_width[2];
|
||||
r = hose->regions;
|
||||
|
||||
if (width && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
|
||||
printf("\n PCIE3 connected as %s (x%d)",
|
||||
host ? "Root Complex" : "End Point", width);
|
||||
if (pci->pme_msg_det) {
|
||||
pci->pme_msg_det = 0xffffffff;
|
||||
debug(" with errors. Clearing. Now 0x%08x",
|
||||
pci->pme_msg_det);
|
||||
}
|
||||
printf("\n");
|
||||
|
||||
/* inbound */
|
||||
r += fsl_pci_setup_inbound_windows(r);
|
||||
|
||||
/* outbound memory */
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE3_MEM_BASE,
|
||||
CONFIG_SYS_PCIE3_MEM_PHYS,
|
||||
CONFIG_SYS_PCIE3_MEM_SIZE,
|
||||
PCI_REGION_MEM);
|
||||
|
||||
/* outbound io */
|
||||
pci_set_region(r++,
|
||||
CONFIG_SYS_PCIE3_IO_BASE,
|
||||
CONFIG_SYS_PCIE3_IO_PHYS,
|
||||
CONFIG_SYS_PCIE3_IO_SIZE,
|
||||
PCI_REGION_IO);
|
||||
|
||||
hose->region_count = r - hose->regions;
|
||||
|
||||
hose->first_busno = first_free_busno;
|
||||
pci_setup_indirect(hose, (int)&pci->cfg_addr,
|
||||
(int)&pci->cfg_data);
|
||||
|
||||
fsl_pci_init(hose);
|
||||
first_free_busno = hose->last_busno+1;
|
||||
printf(" PCIE3 on bus %02x - %02x\n",
|
||||
hose->first_busno, hose->last_busno);
|
||||
}
|
||||
#else
|
||||
gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
|
||||
#endif /* CONFIG_PCIE3 */
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
|
||||
struct pci_controller *hose);
|
||||
|
||||
void ft_board_pci_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
#ifdef CONFIG_PCIE1
|
||||
ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE2
|
||||
ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
|
||||
#endif
|
||||
#ifdef CONFIG_PCIE3
|
||||
ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_OF_BOARD_SETUP */
|
||||
Reference in New Issue
Block a user