Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
This commit is contained in:
@@ -326,6 +326,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS)
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puts("Work-around for Erratum XFI on B4860QDS enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009663
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puts("Work-around for Erratum A009663 enabled\n");
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#endif
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return 0;
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}
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@@ -31,6 +31,9 @@
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#include <hwconfig.h>
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#include <linux/compiler.h>
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#include "mp.h"
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#ifdef CONFIG_CHAIN_OF_TRUST
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#include <fsl_validate.h>
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#endif
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#ifdef CONFIG_FSL_CAAM
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#include <fsl_sec.h>
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#endif
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@@ -1020,3 +1023,14 @@ void cpu_secondary_init_r(void)
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qe_reset();
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#endif
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#ifdef CONFIG_CHAIN_OF_TRUST
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fsl_setenv_chain_of_trust();
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#endif
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return 0;
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}
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#endif
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@@ -808,6 +808,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
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#define QE_NUM_OF_SNUM 28
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#define CONFIG_SYS_FSL_SFP_VER_3_0
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#define CONFIG_SYS_FSL_ERRATUM_A008378
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#define CONFIG_SYS_FSL_ERRATUM_A009663
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#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
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defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
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@@ -856,6 +857,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
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#define QE_NUM_OF_SNUM 28
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#define CONFIG_SYS_FSL_SFP_VER_3_0
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#define CONFIG_SYS_FSL_ERRATUM_A008378
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#define CONFIG_SYS_FSL_ERRATUM_A009663
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#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
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#define CONFIG_E6500
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@@ -9,18 +9,11 @@
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#include <asm/config_mpc85xx.h>
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#ifdef CONFIG_SECURE_BOOT
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#define CONFIG_CMD_ESBC_VALIDATE
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#define CONFIG_FSL_SEC_MON
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#define CONFIG_SHA_PROG_HW_ACCEL
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#define CONFIG_DM
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#define CONFIG_RSA
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#define CONFIG_RSA_FREESCALE_EXP
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#ifndef CONFIG_FSL_CAAM
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#define CONFIG_FSL_CAAM
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#endif
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#ifndef CONFIG_FIT_SIGNATURE
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#define CONFIG_CHAIN_OF_TRUST
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#endif
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#ifdef CONFIG_SECURE_BOOT
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#if defined(CONFIG_FSL_CORENET)
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#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
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#elif defined(CONFIG_BSC9132QDS)
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@@ -75,8 +68,32 @@
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*/
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#define CONFIG_FSL_ISBC_KEY_EXT
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#endif
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#endif /* #ifdef CONFIG_SECURE_BOOT */
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#ifdef CONFIG_CHAIN_OF_TRUST
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#define CONFIG_CMD_ESBC_VALIDATE
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#define CONFIG_CMD_BLOB
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#define CONFIG_FSL_SEC_MON
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#define CONFIG_SHA_PROG_HW_ACCEL
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#define CONFIG_RSA
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#define CONFIG_RSA_FREESCALE_EXP
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#ifndef CONFIG_DM
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#define CONFIG_DM
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#endif
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#ifndef CONFIG_FSL_CAAM
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#define CONFIG_FSL_CAAM
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#endif
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/* fsl_setenv_chain_of_trust() must be called from
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* board_late_init()
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*/
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#ifndef CONFIG_BOARD_LATE_INIT
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#define CONFIG_BOARD_LATE_INIT
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#endif
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#ifndef CONFIG_FIT_SIGNATURE
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/* If Boot Script is not on NOR and is required to be copied on RAM */
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#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
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#define CONFIG_BS_HDR_ADDR_RAM 0x00010000
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@@ -104,10 +121,8 @@
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
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#endif
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#endif
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#endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
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#include <config_fsl_secboot.h>
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#endif
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#endif
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#include <config_fsl_chain_trust.h>
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#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
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#endif
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@@ -1749,6 +1749,8 @@ typedef struct ccsr_gur {
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u32 brrl; /* Boot release */
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u8 res17[24];
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u32 rcwsr[16]; /* Reset control word status */
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#define RCW_SB_EN_REG_INDEX 7
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#define RCW_SB_EN_MASK 0x00200000
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#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
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#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT 16
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@@ -2194,6 +2196,7 @@ typedef struct ccsr_gur {
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#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008
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#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3
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#endif
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#define MPC85xx_PORDEVSR2_SBC_MASK 0x10000000
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/* The 8544 RM says this is bit 26, but it's really bit 24 */
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#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080
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u8 res1[8];
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