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sh: sh3: Remove CPU support

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This CPU core is old, no boards using the CPU are left in mainline,
it has no prospects of ever being converted to DM, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
This commit is contained in:
Marek Vasut
2019-05-07 22:04:05 +02:00
committed by Marek Vasut
parent 89a6b74636
commit d0487da83f
16 changed files with 9 additions and 581 deletions
Download Patch File Download Diff File Expand all files Collapse all files

75
drivers/serial/serial_sh.h
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@@ -12,28 +12,7 @@ struct uart_port {
enum sh_clk_mode clk_mode; /* clock mode */
};
#if defined(CONFIG_CPU_SH7706) || \
defined(CONFIG_CPU_SH7707) || \
defined(CONFIG_CPU_SH7708) || \
defined(CONFIG_CPU_SH7709)
# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
#elif defined(CONFIG_CPU_SH7705)
# define SCIF0 0xA4400000
# define SCIF2 0xA4410000
# define SCSMR_Ir 0xA44A0000
# define IRDA_SCIF SCIF0
# define SCPCR 0xA4000116
# define SCPDR 0xA4000136
/* Set the clock source,
* SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
* SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
*/
# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
#elif defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
@@ -51,12 +30,6 @@ struct uart_port {
# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */)
#elif defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
# define SCIF_ORER 0x0001 /* overrun error bit */
# define PACR 0xa4050100
# define PBCR 0xa4050102
# define SCSCR_INIT(port) 0x3B
#elif defined(CONFIG_CPU_SH7722)
# define PADR 0xA4050120
# undef PSDR
@@ -175,9 +148,7 @@ struct uart_port {
#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
#if defined(CONFIG_CPU_SH7705) || \
defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
# define SCIF_ORER 0x0200
@@ -225,9 +196,7 @@ struct uart_port {
#define SCxSR_ORER(port)\
(((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
#if defined(CONFIG_CPU_SH7705) || \
defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
@@ -309,23 +278,9 @@ static inline void sci_##name##_out(struct uart_port *port,\
SCI_OUT(sci_size, sci_offset, value);\
}
#if defined(CONFIG_CPU_SH3) || \
defined(CONFIG_SH73A0) || \
#if defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
#if defined(CONFIG_CPU_SH7710) || defined(CONFIG_CPU_SH7712)
#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size,\
sh4_sci_offset, sh4_sci_size, \
sh3_scif_offset, sh3_scif_size, \
sh4_scif_offset, sh4_scif_size, \
h8_sci_offset, h8_sci_size) \
CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size,\
sh4_scif_offset, sh4_scif_size)
#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size,\
sh4_scif_offset, sh4_scif_size) \
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
#elif defined(CONFIG_CPU_SH7705) || \
defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0)
#define SCIF_FNS(name, scif_offset, scif_size) \
CPU_SCIF_FNS(name, scif_offset, scif_size)
@@ -368,9 +323,7 @@ static inline void sci_##name##_out(struct uart_port *port,\
CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
#endif
#if defined(CONFIG_CPU_SH7705) || \
defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
#if defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0)
SCIF_FNS(SCSMR, 0x00, 16)
@@ -471,17 +424,7 @@ SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */
#define sci_in(port, reg) sci_##reg##_in(port)
#define sci_out(port, reg, value) sci_##reg##_out(port, value)
#if defined(CONFIG_CPU_SH7706) || \
defined(CONFIG_CPU_SH7707) || \
defined(CONFIG_CPU_SH7708) || \
defined(CONFIG_CPU_SH7709)
static inline int sci_rxd_in(struct uart_port *port)
{
if (port->mapbase == 0xfffffe80)
return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
return 1;
}
#elif defined(CONFIG_CPU_SH7750) || \
#if defined(CONFIG_CPU_SH7750) || \
defined(CONFIG_CPU_SH7751) || \
defined(CONFIG_CPU_SH7751R) || \
defined(CONFIG_CPU_SH7750R) || \
@@ -533,9 +476,7 @@ static inline int sci_rxd_in(struct uart_port *port)
#if defined(CONFIG_CPU_SH7780)
#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
#elif defined(CONFIG_CPU_SH7705) || \
defined(CONFIG_CPU_SH7720) || \
defined(CONFIG_CPU_SH7721) || \
#elif defined(CONFIG_CPU_SH7721) || \
defined(CONFIG_SH73A0) || \
defined(CONFIG_R8A7740)
#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)