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ppc4xx: Big cleanup of PPC4xx defines

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This patch cleans up multiple issues of the 4xx register (mostly
DCR, SDR, CPR, etc) definitions:

- Change lower case defines to upper case (plb4_acr -> PLB4_ACR)
- Change the defines to better match the names from the
  user's manuals (e.g. cprpllc -> CPR0_PLLC)
- Removal of some unused defines

Please test this patch intensive on your PPC4xx platform. Even though
I tried not to break anything and tested successfully on multiple
4xx AMCC platforms, testing on custom platforms is recommended.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
2009-09-09 16:25:29 +02:00
parent e7963772eb
commit d1c3b27525
128 changed files with 2086 additions and 2397 deletions
Download Patch File Download Diff File Expand all files Collapse all files

50
post/cpu/ppc4xx/ether.c
View File

@@ -109,9 +109,9 @@ static void ether_post_init (int devnum, int hw_addr)
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* provide clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfsdr (SDR0_MFR, mfr);
mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
mtsdr (sdr_mfr, mfr);
mtsdr (SDR0_MFR, mfr);
sync ();
#endif
/* reset emac */
@@ -150,13 +150,13 @@ static void ether_post_init (int devnum, int hw_addr)
#if defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
MAL_CR_PLBLT_DEFAULT | 0x00330000);
#else
mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
/* Errata 1.12: MAL_1 -- Disable MAL bursting */
if (get_pvr() == PVR_440GP_RB) {
mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB);
}
#endif
/* setup buffer descriptors */
@@ -174,39 +174,39 @@ static void ether_post_init (int devnum, int hw_addr)
case 1:
/* setup MAL tx & rx channel pointers */
#if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
mtdcr (maltxctp2r, &tx);
mtdcr (MAL0_TXCTP2R, &tx);
#else
mtdcr (maltxctp1r, &tx);
mtdcr (MAL0_TXCTP1R, &tx);
#endif
#if defined(CONFIG_440)
mtdcr (maltxbattr, 0x0);
mtdcr (malrxbattr, 0x0);
mtdcr (MAL0_TXBADDR, 0x0);
mtdcr (MAL0_RXBADDR, 0x0);
#endif
mtdcr (malrxctp1r, &rx);
mtdcr (MAL0_RXCTP1R, &rx);
/* set RX buffer size */
mtdcr (malrcbs1, PKTSIZE_ALIGN / 16);
mtdcr (MAL0_RCBS1, PKTSIZE_ALIGN / 16);
break;
case 0:
default:
/* setup MAL tx & rx channel pointers */
#if defined(CONFIG_440)
mtdcr (maltxbattr, 0x0);
mtdcr (malrxbattr, 0x0);
mtdcr (MAL0_TXBADDR, 0x0);
mtdcr (MAL0_RXBADDR, 0x0);
#endif
mtdcr (maltxctp0r, &tx);
mtdcr (malrxctp0r, &rx);
mtdcr (MAL0_TXCTP0R, &tx);
mtdcr (MAL0_RXCTP0R, &rx);
/* set RX buffer size */
mtdcr (malrcbs0, PKTSIZE_ALIGN / 16);
mtdcr (MAL0_RCBS0, PKTSIZE_ALIGN / 16);
break;
}
/* Enable MAL transmit and receive channels */
#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
mtdcr (maltxcasr, (MAL_TXRX_CASR >> (devnum*2)));
mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (devnum*2)));
#else
mtdcr (maltxcasr, (MAL_TXRX_CASR >> devnum));
mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> devnum));
#endif
mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum));
mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> devnum));
/* set internal loopback mode */
#ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK
@@ -257,14 +257,14 @@ static void ether_post_halt (int devnum, int hw_addr)
/* 1st reset MAL channel */
/* Note: writing a 0 to a channel has no effect */
#if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
mtdcr (maltxcarr, MAL_TXRX_CASR >> (devnum * 2));
mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> (devnum * 2));
#else
mtdcr (maltxcarr, MAL_TXRX_CASR >> devnum);
mtdcr (MAL0_TXCARR, MAL_TXRX_CASR >> devnum);
#endif
mtdcr (malrxcarr, MAL_TXRX_CASR >> devnum);
mtdcr (MAL0_RXCARR, MAL_TXRX_CASR >> devnum);
/* wait for reset */
while (mfdcr (malrxcasr) & (MAL_TXRX_CASR >> devnum)) {
while (mfdcr (MAL0_RXCASR) & (MAL_TXRX_CASR >> devnum)) {
if (i++ >= 1000)
break;
udelay (1000);
@@ -274,9 +274,9 @@ static void ether_post_halt (int devnum, int hw_addr)
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* remove clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr);
mfsdr (SDR0_MFR, mfr);
mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
mtsdr (sdr_mfr, mfr);
mtsdr (SDR0_MFR, mfr);
#endif
}

22
post/cpu/ppc4xx/uart.c
View File

@@ -68,7 +68,7 @@
#define CR0_EXTCLK_ENA 0x00600000
#define CR0_UDIV_POS 16
#define UDIV_SUBTRACT 1
#define UART0_SDR cntrl0
#define UART0_SDR CPC0_CR0
#define MFREG(a, d) d = mfdcr(a)
#define MTREG(a, d) mtdcr(a, d)
#else /* #if defined(CONFIG_440GP) */
@@ -77,16 +77,16 @@
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
#define UDIV_SUBTRACT 0
#define UART0_SDR sdr_uart0
#define UART1_SDR sdr_uart1
#define UART0_SDR SDR0_UART0
#define UART1_SDR SDR0_UART1
#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP) || defined(CONFIG_440SPE)
#define UART2_SDR sdr_uart2
#define UART2_SDR SDR0_UART2
#endif
#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GR) || defined(CONFIG_440GRX)
#define UART3_SDR sdr_uart3
#define UART3_SDR SDR0_UART3
#endif
#define MFREG(a, d) mfsdr(a, d)
#define MTREG(a, d) mtsdr(a, d)
@@ -106,8 +106,8 @@
#define CR0_EXTCLK_ENA 0x00800000
#define CR0_UDIV_POS 0
#define UDIV_SUBTRACT 0
#define UART0_SDR sdr_uart0
#define UART1_SDR sdr_uart1
#define UART0_SDR SDR0_UART0
#define UART1_SDR SDR0_UART1
#define MFREG(a, d) mfsdr(a, d)
#define MTREG(a, d) mtsdr(a, d)
#else /* CONFIG_405GP || CONFIG_405CR */
@@ -276,7 +276,7 @@ static int uart_post_init (unsigned long dev_base)
clk = tmp = reg = 0;
#else
#ifdef CONFIG_405EP
reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
clk = gd->cpu_clk;
tmp = CONFIG_SYS_BASE_BAUD * 16;
udiv = (clk + tmp / 2) / tmp;
@@ -284,9 +284,9 @@ static int uart_post_init (unsigned long dev_base)
udiv = UDIV_MAX;
reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
mtdcr (cpc0_ucr, reg);
mtdcr (CPC0_UCR, reg);
#else /* CONFIG_405EP */
reg = mfdcr(cntrl0) & ~CR0_MASK;
reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
udiv = 1;
@@ -303,7 +303,7 @@ static int uart_post_init (unsigned long dev_base)
#endif
#endif
reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
mtdcr (cntrl0, reg);
mtdcr (CPC0_CR0, reg);
#endif /* CONFIG_405EP */
tmp = gd->baudrate * udiv * 16;
bdiv = (clk + tmp / 2) / tmp;