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arm64: dts: rockchip: Add SARADC node for RK3528

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Add a device tree node for the SARADC controller used by RK3528.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20250304201642.831218-4-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

[ upstream commit: 6e58302c84ce90aadbecd41efe1f69098a6f91e5 ]

(cherry picked from commit 8ba64ba5cb301bca777ba7f0d2a2a72f49af5ff2)
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Jonas Karlman
2025-04-07 22:46:40 +00:00
committed by Simon Glass
parent 8b04183cbd
commit d3c396824a
1 changed files with 13 additions and 0 deletions
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13
dts/upstream/src/arm64/rockchip/rk3528.dtsi
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@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rockchip,rk3528-cru.h>
#include <dt-bindings/reset/rockchip,rk3528-cru.h>
/ {
compatible = "rockchip,rk3528";
@@ -455,6 +456,18 @@
status = "disabled";
};
saradc: adc@ffae0000 {
compatible = "rockchip,rk3528-saradc";
reg = <0x0 0xffae0000 0x0 0x10000>;
clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
resets = <&cru SRST_P_SARADC>;
reset-names = "saradc-apb";
#io-channel-cells = <1>;
status = "disabled";
};
pinctrl: pinctrl {
compatible = "rockchip,rk3528-pinctrl";
rockchip,grf = <&ioc_grf>;