arm: imx: Add support for Google's Coral Dev Board
Add initial support for Google's Coral Dev Board based on i.MX8MQ. https://coral.ai/products/dev-board The Phanbell naming has been used here to match the naming convention used in Google's U-Boot source tree: https://coral.googlesource.com/uboot-imx/ Co-developed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com> Tested-by: Marco Franchi <marcofrk@gmail.com>
This commit is contained in:
Alifer Moraes
committed by
Stefano Babic
Stefano Babic
parent
d304e7ace3
commit
ef99f3d9e8
12
board/google/imx8mq_phanbell/Kconfig
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12
board/google/imx8mq_phanbell/Kconfig
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@@ -0,0 +1,12 @@
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if TARGET_IMX8MQ_PHANBELL
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config SYS_BOARD
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default "imx8mq_phanbell"
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config SYS_VENDOR
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default "google"
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config SYS_CONFIG_NAME
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default "imx8mq_phanbell"
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endif
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8
board/google/imx8mq_phanbell/MAINTAINERS
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8
board/google/imx8mq_phanbell/MAINTAINERS
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i.MX 8MQ PHANBELL BOARD
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M: Fabio Estevam <festevam@gmail.com>
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M: Marco Franchi <marcofrk@gmail.com>
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M: Alifer Moraes <alifer.wsdm@gmail.com>
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S: Maintained
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F: board/google/imx8mq_phanbell/
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F: include/configs/imx8mq_phanbell.h
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F: configs/imx8mq_phanbell_defconfig
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11
board/google/imx8mq_phanbell/Makefile
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11
board/google/imx8mq_phanbell/Makefile
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2020 NXP
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#
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obj-y += imx8mq_phanbell.o
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing_1g.o
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endif
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37
board/google/imx8mq_phanbell/README
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37
board/google/imx8mq_phanbell/README
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@@ -0,0 +1,37 @@
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U-Boot for Google's i.MX8MQ Phanbell board
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Quick Start
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===========
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- Build the ARM Trusted firmware binary
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- Get ddr and hdmi firmware
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- Build U-Boot
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- Boot
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Get and Build the ARM Trusted firmware
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======================================
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Note: srctree is U-Boot source directory
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Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
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branch: imx_4.19.35_1.0.0
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$ make PLAT=imx8mq bl31
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$ cp build/imx8mq/release/bl31.bin $(builddir)
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Get the ddr and hdmi firmware
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=============================
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$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
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$ chmod +x firmware-imx-7.9.bin
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$ ./firmware-imx-7.9.bin
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$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(builddir)
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$ cp firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
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Build U-Boot
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============
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$ export CROSS_COMPILE=aarch64-linux-gnu-
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$ make imx8mq_phanbell_defconfig
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$ make flash.bin
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Burn the flash.bin to MicroSD card offset 33KB
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$sudo dd if=flash.bin of=/dev/sd[x] bs=1K seek=33
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Boot
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====
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Set Boot switch SW1: 1011 to boot from Micro SD.
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100
board/google/imx8mq_phanbell/imx8mq_phanbell.c
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100
board/google/imx8mq_phanbell/imx8mq_phanbell.c
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@@ -0,0 +1,100 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 NXP
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*/
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#include <common.h>
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#include <env.h>
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#include <init.h>
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#include <malloc.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm-generic/gpio.h>
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#include <fsl_esdhc_imx.h>
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#include <mmc.h>
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#include <asm/arch/imx8mq_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm/arch/clock.h>
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#include <spl.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
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#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
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static iomux_v3_cfg_t const wdog_pads[] = {
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IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
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};
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static iomux_v3_cfg_t const uart_pads[] = {
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IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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int board_early_init_f(void)
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{
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struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
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imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
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set_wdog_reset(wdog);
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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return 0;
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}
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int dram_init(void)
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{
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/* rom_pointer[1] contains the size of TEE occupies */
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if (rom_pointer[1])
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gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
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else
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gd->ram_size = PHYS_SDRAM_SIZE;
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return 0;
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}
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#ifdef CONFIG_FEC_MXC
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static int setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* Use 125M anatop REF_CLK1 for ENET1, not from external */
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clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
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return set_clk_enet(ENET_125MHZ);
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}
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int board_phy_config(struct phy_device *phydev)
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{
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/* enable rgmii rxc skew and phy mode select to RGMII copper */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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int board_init(void)
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{
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#ifdef CONFIG_FEC_MXC
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setup_fec();
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#endif
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return 0;
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}
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int board_mmc_get_env_dev(int devno)
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{
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return devno;
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}
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1731
board/google/imx8mq_phanbell/lpddr4_timing_1g.c
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1731
board/google/imx8mq_phanbell/lpddr4_timing_1g.c
Normal file
File diff suppressed because it is too large
Load Diff
180
board/google/imx8mq_phanbell/spl.c
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180
board/google/imx8mq_phanbell/spl.c
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@@ -0,0 +1,180 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2020 NXP
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*
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*/
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#include <common.h>
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#include <hang.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/imx8mq_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/clock.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/gpio.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/sections.h>
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#include <fsl_esdhc_imx.h>
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#include <mmc.h>
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#include <spl.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void spl_dram_init(void)
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{
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/* ddr init */
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ddr_init(&dram_timing);
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}
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#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
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#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
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#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret = 0;
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switch (cfg->esdhc_base) {
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case USDHC1_BASE_ADDR:
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ret = 1;
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break;
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case USDHC2_BASE_ADDR:
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ret = !gpio_get_value(USDHC2_CD_GPIO);
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return ret;
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}
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return 1;
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}
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#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
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PAD_CTL_FSEL2)
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#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
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static iomux_v3_cfg_t const usdhc1_pads[] = {
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IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const usdhc2_pads[] = {
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IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
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IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
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IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
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IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
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IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
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IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
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IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
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IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
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};
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static struct fsl_esdhc_cfg usdhc_cfg[2] = {
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{USDHC1_BASE_ADDR},
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{USDHC2_BASE_ADDR},
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};
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int board_mmc_init(bd_t *bis)
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{
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int i, ret;
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/*
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* According to the board_mmc_init() the following map is done:
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* (U-Boot device node) (Physical Port)
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* mmc0 USDHC1
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* mmc1 USDHC2
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*/
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for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
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switch (i) {
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case 0:
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init_clk_usdhc(0);
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usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
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usdhc_cfg[0].max_bus_width = 8;
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imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
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ARRAY_SIZE(usdhc1_pads));
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gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
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gpio_direction_output(USDHC1_PWR_GPIO, 0);
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udelay(500);
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gpio_direction_output(USDHC1_PWR_GPIO, 1);
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break;
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case 1:
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init_clk_usdhc(1);
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usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
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usdhc_cfg[1].max_bus_width = 4;
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imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
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ARRAY_SIZE(usdhc2_pads));
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gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
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gpio_direction_output(USDHC2_PWR_GPIO, 0);
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udelay(500);
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gpio_direction_output(USDHC2_PWR_GPIO, 1);
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break;
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default:
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printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
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if (ret)
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return ret;
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}
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return 0;
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}
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void spl_board_init(void)
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{
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puts("Normal Boot\n");
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}
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* Just empty function now - can't decide what to choose */
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debug("%s: %s\n", __func__, name);
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return 0;
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}
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#endif
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void board_init_f(ulong dummy)
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{
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int ret;
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/* Clear global data */
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memset((void *)gd, 0, sizeof(gd_t));
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arch_cpu_init();
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init_uart_clk(0);
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board_early_init_f();
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timer_init();
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preloader_console_init();
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/* Clear the BSS. */
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memset(__bss_start, 0, __bss_end - __bss_start);
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ret = spl_init();
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if (ret) {
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debug("spl_init() failed: %d\n", ret);
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hang();
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}
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enable_tzc380();
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/* DDR initialization */
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spl_dram_init();
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board_init_r(NULL, 0);
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}
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