smallsolar/u-boot
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

83xx/85xx/86xx: LBC register cleanup

Browse Source 
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers.  Merge
this into a single spot.

To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.

In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.

I have done a successful ppc build all and tested a board or two from
each processor family.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Becky Bruce
2010-06-17 11:37:20 -05:00
committed by Kumar Gala
parent 0914f48328
commit f51cdaf191
52 changed files with 317 additions and 499 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
board/socrates/socrates.c
View File

@@ -87,8 +87,6 @@ int checkboard (void)
int misc_init_r (void)
{
volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
/*
* Adjust flash start and offset to detected values
*/
@@ -99,8 +97,10 @@ int misc_init_r (void)
* Check if boot FLASH isn't max size
*/
if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
memctl->or0 = gd->bd->bi_flashstart | (CONFIG_SYS_OR0_PRELIM & 0x00007fff);
memctl->br0 = gd->bd->bi_flashstart | (CONFIG_SYS_BR0_PRELIM & 0x00007fff);
set_lbc_or(0, gd->bd->bi_flashstart |
(CONFIG_SYS_OR0_PRELIM & 0x00007fff));
set_lbc_br(0, gd->bd->bi_flashstart |
(CONFIG_SYS_BR0_PRELIM & 0x00007fff));
/*
* Re-check to get correct base address
@@ -112,8 +112,8 @@ int misc_init_r (void)
* Check if only one FLASH bank is available
*/
if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
memctl->or1 = 0;
memctl->br1 = 0;
set_lbc_or(1, 0);
set_lbc_br(1, 0);
/*
* Re-do flash protection upon new addresses
@@ -148,7 +148,7 @@ int misc_init_r (void)
*/
void local_bus_init (void)
{
volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
sys_info_t sysinfo;
uint clkdiv;
@@ -299,26 +299,25 @@ const gdc_regs *board_get_regs (void)
int lime_probe(void)
{
volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
uint cfg_br2;
uint cfg_or2;
int type;
cfg_br2 = memctl->br2;
cfg_or2 = memctl->or2;
cfg_br2 = get_lbc_br(2);
cfg_or2 = get_lbc_or(2);
/* Configure GPCM for CS2 */
memctl->br2 = 0;
memctl->or2 = 0xfc000410;
memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901;
set_lbc_br(2, 0);
set_lbc_or(2, 0xfc000410);
set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901);
/* Get controller type */
type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
/* Restore previous CS2 configuration */
memctl->br2 = 0;
memctl->or2 = cfg_or2;
memctl->br2 = cfg_br2;
set_lbc_br(2, 0);
set_lbc_or(2, cfg_or2);
set_lbc_br(2, cfg_br2);
return (type == MB862XX_TYPE_LIME) ? 1 : 0;
}