Bryan Brattlof <bb@ti.com> says:
Hello Everyone!
This small series converts TI's AM65x reference board to use
CONFIG_OF_UPSTREAM and removes the unused device tree files from
arch/arm/dts.
Because it's the last board using a AM65x without enabling OF_UPSTREAM
it allows us to also remove all the SoC FDT files as well and keep a
single version of the SoC's DT files in the dts/upstream directory going
forward.
Link: https://lore.kernel.org/r/20241121-am65x-v1-0-fe87aff1b5fc@ti.com
(cherry picked from commit 39759bf9fe)
With all boards using TI's AM65x having enabled CONFIG_OF_UPSTREAM
cleanup the unused SoC fdt files.
Signed-off-by: Bryan Brattlof <bb@ti.com>
(cherry picked from commit 1c7c5b09cd)
With the reference board now using CONFIG_OF_UPSTREAM these board files
are unused. Remove them
Signed-off-by: Bryan Brattlof <bb@ti.com>
(cherry picked from commit 688dfb9234)
Rather than rely on manual updates from the arch/arm/dts directory,
enable CONFIG_OF_UPSTREAM to receive automatic device tree updates for
the am65x reference board.
Signed-off-by: Bryan Brattlof <bb@ti.com>
(cherry picked from commit 262a62ad93)
Based on the recommendation from HW team make modifications to
the sequence for more robustness.
- Unlock the PLL registers
- Enable external bypass
- Disable the PLL
- Program pllm and pllf
- Program Ref divider
- Enable other PLL controls like DSM_EN, DAC_EN,etc
- Enable calibration if available
- Enable PLL
- Wait for PLL lock and Calibration lock
- Remove external bypass
Re-write the full sequence from scratch as the previous sequence was way
off and keep it in a single commit for bisectability.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
(cherry picked from commit 79d91e77f4)
base is more appropriate for the usage as the variable stores the base
address and seems more accurate w.r.t reg. Change reg to base.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
(cherry picked from commit d6cd643c4e)
Updated PLL driver sequencing requires us to use udelay in the PLL
driver as there is no poll bit to get the status of operations.
tick-timer(mcu_timer0/main_timer0) setting up the clocks for itself is
something that won't work as the PLL driver will be using udelay and
PLLs are configured during clock probe which would end up in a recursive
probe.
tick-timer being used by K3 devices are configured by ROM and we really
don't need to configure any of the clocks.
Remove the clock dependency from R5 stage as we don't need to setup
clocks for it.
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>
(cherry picked from commit 5d1aac358f)
Switch the callback static list from the board configuration variable
CFG_ENV_CALLBACK_LIST_STATIC to Kconfig CONFIG_ENV_CALLBACK_LIST_STATIC.
Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Reviewed-by: Marek Vasut <marex@denx.de>
(cherry picked from commit dca82739b9)
Those debug() calls might be useful, but beware. They can cause the DDR
controller to hang if we do not run the sequence quickly enough.
They usually are not an issue with upstream U-Boot and the default DDR
config, but they have become troublesome with custom DDR configs.
Drop those debug() statements that shouldn't be present in
time-sensitive code, to avoid anyone else falling into the trap.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
(cherry picked from commit ce05ec4895)
Aniket Limaye <a-limaye@ti.com> says:
This series adds OPP_LOW spec data in k3_avs driver and enables a config
option to select the OPP_LOW performance point.
J7200 SOC supports OPP_LOW and OPP_NOM as two Operating Performance
Points as per (7.5 Operating Performance Points) section in the
Datasheet [0].
- A72SS/MSMC at 2 GHz/1GHz operation must use OPP_NOM.
- A72SS/MSMC at 1 GHz/500 MHz operation can use OPP_NOM or OPP_LOW
voltage (though OPP_LOW voltage is recommended to reduce power
consumption).
The actual OPP voltage for the device is read from the efuse and
updated in k3_avs_probe().
The default j7200 devicetree and k3_avs driver set OPP_NOM spec
frequency and voltage.
In the board init file, if K3_OPP_LOW config is enabled, Check if
OPP_LOW AVS voltage read from efuse is valid and update frequency (A72
and MSMC) and voltage (VDD_CPU) as per the OPP_LOW spec.
[0]: https://www.ti.com/lit/gpn/dra821u (J7200 Datasheet)
Test logs:
https://gist.github.com/aniket-l/328ad93ed60c2419ed7be9f85e6b6075
- With series applied on master and CONFIG_K3_OPP_LOW enabled in
j7200_evm_r5_defconfig
- Logs shown with and without efuse register programmed for OPP_0
(Errors out if OPP_0 not found, programs OPP_LOW spec if found)
- Voltage update verified using 'i2c md 0x4c 0xe' in u-boot
- Frequency update verified using 'k3conf clock dump' in linux
Link: https://lore.kernel.org/r/20241119003617.1871183-1-a-limaye@ti.com
(cherry picked from commit fe76d868f7)
Define new CONFIG_K3_OPP_LOW under arm/mach-k3/r5/Kconfig and add
default value to j7200_evm_r5_defconfig
Signed-off-by: Reid Tonking <reidt@ti.com>
Signed-off-by: Aniket Limaye <a-limaye@ti.com>
(cherry picked from commit abb2544d89)
The default j7200 devicetree and k3_avs driver set 2GHz/1GHz frequency
for A72/MSMC clks and the OPP_NOM voltage.
J7200 SOCs may support OPP_LOW Operating Performance Point:
1GHz/500MHz clks for A72/MSMC and OPP_LOW AVS voltage read from efuse.
Hence, add a config check in board_init_f() to select OPP_LOW specs:
- Check if OPP_LOW AVS voltage read from efuse is valid.
- Use the device IDs and clock IDs (TISCI docs [0]) to find the A72 and
MSMC clock frequencies in the devicetree.
- Fixup the clock frequencies in devicetree as per OPP_LOW spec.
k3_avs driver programs the OPP_LOW AVS voltage for VDD_CPU through
k3_avs_notify_freq() callback from clk_k3.
[0]: https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j7200/clocks.html
Signed-off-by: Aniket Limaye <a-limaye@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
(cherry picked from commit 82ab094c1a)
k3_avs driver checks opp_ids when probing and overwrites the voltage
values in vd_data for the respective board. The new k3_avs_check_opp()
can be called from board files to check the efuse data and returns 0 if
valid.
Also add the same check in k3_avs_program_voltage() to error out if
the efuse data was not valid.
Signed-off-by: Reid Tonking <reidt@ti.com>
Signed-off-by: Aniket Limaye <a-limaye@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
(cherry picked from commit afe0ab6d30)
J7200 SOC supports OPP_LOW and OPP_NOM as two Operating Performance
Points as per (7.5 Operating Performance Points) section in the
Datasheet [0].
- A72SS/MSMC at 2 GHz/1GHz operation must use OPP_NOM.
- A72SS/MSMC at 1 GHz/500 MHz operation can use OPP_NOM or OPP_LOW
voltage (though OPP_LOW voltage is recommended to reduce power
consumption).
Add OPP_LOW frequency->voltage entry to vd_data.
The actual OPP voltage for the device is read from the efuse and
updated in k3_avs_probe().
OPP_NOM corresponds to OPP_1 and OPP_LOW to OPP_0 efuse register
fields, as described in the Datasheet [0]
The register offsets and fields are described in the TRM (5.2.6.1.5
WKUP_VTM_VD_OPPVID_j Register) [1].
[0]: https://www.ti.com/lit/gpn/dra821u (J7200 Datasheet)
[1]: https://www.ti.com/lit/pdf/spruiu1 (J7200 TRM)
Signed-off-by: Reid Tonking <reidt@ti.com>
Signed-off-by: Aniket Limaye <a-limaye@ti.com>
(cherry picked from commit 287a3b25bd)
Enable AVS support on J784S4 along with regulator.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
(cherry picked from commit 368bb08998)
Probe the AVS driver to set the AVS voltage.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
(cherry picked from commit 6f6192f626)
Add the VTM node to the R5 boot stage so that AVS is correctly
configured for AM68 SK.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
(cherry picked from commit d43d612469)
Add VTM node to R5 boot stage so that AVS gets correctly configured for
J784S4 EVM and AM69 SK.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
(cherry picked from commit 480f6531ab)
Currently in _dm_gpio_set_flags() when set_flags ops is not implemented
direction_output()/_input() is used, but pull up/down is not supported by
these ops.
Signed-off-by: Zixun LI <admin@hifiphile.com>
(cherry picked from commit 3c69a95b9a)
Avoid crashing U-Boot when the GPIO controller for a button is disabled
or failed to probe. We also need to check the priv data for each button
since even if a button fails to probe it will still be polled by the
core code.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
(cherry picked from commit 15299fa5dd)
Introduce CONFIG_PHYTEC_K3_DDR_PATCH to make DDR timing patch code
optional for PHYTEC K3 boards. This allows better control over which
boards receive DDR timing patches, rather than compiling the code for
all boards with K3_DDRSS enabled.
Also enable the feature by default for PHYCORE_AM62X_R5.
Signed-off-by: Garrett Giordano <ggiordano@phytec.com>
Reviewed-by: Wadim Egorov <w.egorov@phytec.de>
(cherry picked from commit 893ae07cc9)
The ST M24256E behaves as a regular M24C256, except for the E variant
which uses up another I2C address for Additional Write lockable page.
This page is 64 Bytes long and can contain additional data. Add entry
for it, so users can describe that page in DT. Note that users still
have to describe the main M24C256 area separately as that is on separate
I2C address from this page.
Unlike M24C32-D and M24C64-D, this part is specifically ST and does not
have any comparable M24* counterparts from other vendors, hence the st,
vendor prefix. Furthermore, the part name is M24256E without C between
the 24 and 256, this is not a typo. Finally, there is M24C256-D part,
which does contain 32 Bytes long Additional Write lockable page, which
is a different part and not supported by this patch.
Datasheet: https://www.st.com/resource/en/datasheet/m24256e-f.pdf
From Linux kernel commit:
339cb28b9ee6 ("eeprom: at24: add ST M24256E Additional Write lockable page support")
Signed-off-by: Marek Vasut <marex@denx.de>
(cherry picked from commit dcee0ed33b)
Add efi_dp_from_http to form a device path from HTTP. The
device path is the concatenation of the device path returned
by efi_dp_from_ipv4 together with an URI node and an END node.
Signed-off-by: Adriano Cordova <adrianox@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
This was marked as TODO in the code:
- Enable use of wget_with_dns even if CMD_DNS is disabled if
the given uri has the ip address for the http server.
- Move the check for CMD_DNS inside wget_with_dns.
- Rename wget_with_dns to wget_do_request
Signed-off-by: Adriano Cordova <adrianox@gmail.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
(cherry picked from commit 9bab7d2a7c)
Manuual fixup : pickman created a large diff but the code already exists
Signed-off-by: Simon Glass <simon.glass@canonical.com>
When a timeout occurs while executing a command a 'Boot fail' message is
written and testing is stopped. The user is left in the dark about the
failure cause.
! _pytest.outcomes.Exit: Boot fail: Marking connection bad - no other tests will run !
Add the executed command to the message.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
(cherry picked from commit bc2a1b3c92)
When a timeout occurs while executing a command a 'Lab failure' message is
written and testing is stopped. The user is left in the dark about the
failure cause.
! _pytest.outcomes.Exit: Lab failure: Marking connection bad - no other tests will run !
Add the word 'Timeout' and the executed command to the message.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
(cherry picked from commit 9c7b3dd091)
Always probing pmecc in the generic nand controller probe function and
bailing out if pmecc is missing, prevents the driver to be usable for
SoCs which do not have a pmecc hardware ecc engine like older sam9 SoCs,
for example at91sam9g20. Tested on sam9x60 that the call, which the
comment was moved to, is sufficient to probe the pmecc.
Signed-off-by: Alexander Dahl <ada@thorsis.com>
(cherry picked from commit bf424a110d)
Support GPIO configuration with following flags:
- in, out, out_active
- open_drain, pull_up
Signed-off-by: Zixun LI <admin@hifiphile.com>
(cherry picked from commit 4c178d4061)
This patch adds support for determining whether a gpio pin is mapped as
peripheral function.
Signed-off-by: Zixun LI <admin@hifiphile.com>
(cherry picked from commit e4980192b6)
The bad CRC error message has transposed characters, which render the
output useless:
"bad CRC at record 213: #08x, not #08x" instead of
"bad CRC at record 213: #00000000, not #4be31f4d"
Fix the error message.
Signed-off-by: Benedikt Spranger <b.spranger@linutronix.de>
Reviewed-by: John Ogness <john.ogness@linutronix.de>
(cherry picked from commit 11da3c67e3)
A NULL pointer argument to %s causes a NULL pointer dereference in the
fixed width numerical printout code, since p is overwritten with NULL.
In case of %s width is 0. Check width before dereferencing the pointer.
Signed-off-by: Benedikt Spranger <b.spranger@linutronix.de>
Reviewed-by: John Ogness <john.ogness@linutronix.de>
(cherry picked from commit f0dab28915)
Currently the stage/board selection only works with normal pushes, since
gitlab unfortunately drops CI variables when starting an MR pipeline.
Fix this by looking for tags in the MR description. This only supports
stage-selection, not individual boards.
Simplify the workflow since the previous changes are now not needed.
Cover-letter:
Updates for the new utool
This series includes a patch to make CI work with the way utool
operates, specifically to allow merge requests to honour its requests.
It also drops an unwanted test file.
END
Signed-off-by: Simon Glass <simon.glass@canonical.com>
Prevent automatic merge request pipelines unless UTOOL_TRIGGER=1
is set. This allows utool to create controlled pipelines with
specific CI variables while preventing duplicate automatic pipelines.
Simplify variable name for controlling pytest jobs.
Series-to: concept
Cover-letter:
CI: Tidy up the variables
This series cleans up the variables to make them easier to distinguish
and to avoid duplication.
It also attempts to fix pushing to github.
END
Signed-off-by: Simon Glass <simon.glass@canonical.com>
