pickman: Record review handling for cherry-ddb0f26dc45

(cherry picked from commit 35d9b1d254)

[Cherry-pick fix-up: Empty commit after resolving conflict with deleted gen3-common.c]

.pickman-history

@@ -1017,3 +1017,213 @@ Rebased onto latest ci/master (da67f5e9960). Build verified - sandbox passes.
 
 ---
 
+
+### Review: 2025-12-20
+
+Branch: cherry-ddb0f26dc45
+
+Comments addressed:
+
+
+### Conversation log
+Rebased onto latest ci/master. Build verified OK.
+
+---
+
+### Review: 2025-12-20
+
+Branch: cherry-ddb0f26dc45
+
+Comments addressed:
+
+
+### Conversation log
+Let me find the correct repository location:
+
+I'm already in the u-boot repository. Let me proceed with the rebase:
+
+I can see the branch has 6 commits ahead of the base. The ci/master has moved forward significantly. Let me check the merge base and proceed with the rebase:
+
+Now let me rebase onto ci/master:
+
+The rebase was successful. Let me verify the result:
+
+The rebase was successful - we have 5 commits ahead of ci/master. Note that one of the previous pickman commits was skipped (as it was already applied to ci/master). Now let me run the build verification:
+
+Build succeeded. Now let me check for existing version branches and create the new versioned branch:
+
+There's already a v2 branch, so I need to create v3:
+
+The push failed due to stale info. Let me fetch and retry:
+
+Let me try a direct git push instead:
+
+The push was successful. Let me verify the final state:
+
+## Summary
+
+**Rebase completed successfully** for MR !267 (branch: `cherry-ddb0f26dc45`)
+
+### What was done:
+1. **Checked out** the branch `cherry-ddb0f26dc45`
+2. **Rebased** onto latest `ci/master` using `git rebase --keep-empty ci/master`
+   - Note: One commit (`cffc1f60548 pickman: Record cherry-pick of 4 commits...`) was skipped as it was already applied to ci/master
+3. **Verified build** - sandbox build completed successfully
+4. **Created local branch** `cherry-ddb0f26dc45-v3` for tracking
+5. **Force pushed** to remote `ci/cherry-ddb0f26dc45` to update the MR
+
+### Commits on the rebased branch (5 commits ahead of ci/master):
+1. `7a50cddaeb9` - arm64: Convert core type check macros into inline functions
+2. `a13c388a63f` - arm64: Add MIDR entries for Cortex-A57 and Cortex-A76
+3. `2cee86cd4cf` - arm64: renesas: Convert boards over to is_cortex_a() functions
+4. `347fcc08575` - Merge branch 'master' of u-boot-sh (empty commit)
+5. `8c542accea4` - pickman: Record review handling for cherry-ddb0f26dc45
+
+### Build result:
+- **OK** - sandbox board builds successfully
+
+### Suggested MR reply:
+```
+Rebased onto latest ci/master. Build verified OK.
+
+Pipeline triggered at: https://concept.u-boot.org/u-boot/u-boot/-/merge_requests/267
+```
+
+---
+
+### Review: 2025-12-20
+
+Branch: cherry-ddb0f26dc45
+
+Comments addressed:
+
+
+### Conversation log
+I can see the branch exists. Let me fetch the latest and checkout the branch:
+
+The branch has 6 commits ahead of ci/master. Let me now rebase onto ci/master:
+
+There's a conflict in `.pickman-history`. Let me examine the conflict:
+
+I understand the conflict now. There are two conflicts:
+1. Lines 892-901: Review header sections (cherry-5b5124e3d5c vs cherry-ddb0f26dc45)
+2. Lines 907-1016: Conversation log content
+
+The `.pickman-history` file is a running history log. I need to keep the HEAD content (cherry-5b5124e3d5c entry) and then append the incoming content (cherry-ddb0f26dc45 entry). Let me resolve this:
+
+Now let me resolve the conflict by taking HEAD version and then appending the cherry-ddb0f26dc45 section. The proper resolution is to keep both sections in chronological order:
+
+Now I understand the structure. I need to:
+1. Take the HEAD version completely (which has the cherry-5b5124e3d5c review section)
+2. Append the cherry-ddb0f26dc45 review section from the incoming commit
+
+Let me resolve this properly:
+
+Now I understand. The incoming version has a different base than HEAD. The incoming version has `cherry-6f7f47e8c09` content, while HEAD has `cherry-5b5124e3d5c`. But both files should end up having the `cherry-ddb0f26dc45` review section appended.
+
+Let me check what's in HEAD version:
+
+Good. Now I understand the situation:
+- HEAD has the review for `cherry-5b5124e3d5c` at line 893
+- Incoming has the review for `cherry-ddb0f26dc45` at line 995
+
+The proper resolution is to take HEAD version and append the cherry-ddb0f26dc45 review section. Let me do this:
+
+The rebase completed. Let me verify the result:
+
+The rebase is successful with 6 commits ahead of ci/master. Now let me run the build verification:
+
+Build passed. Now let me check for existing version branches and create the new one:
+
+There's already a v3, so I need to create v4:
+
+Now let me force push to the remote branch to update the MR:
+
+Need to fetch and retry:
+
+Push successful. Let me verify the final state:
+
+## Summary
+
+**Rebase completed successfully** for MR !267 (branch: `cherry-ddb0f26dc45`)
+
+### What was done:
+1. **Checked out** the branch `cherry-ddb0f26dc45`
+2. **Rebased** onto latest `ci/master` using `git rebase --keep-empty ci/master`
+3. **Resolved conflict** in `.pickman-history` - merged the `cherry-5b5124e3d5c` review section (from ci/master) and appended the `cherry-ddb0f26dc45` review section (from this branch)
+4. **Verified build** - sandbox build completed successfully
+5. **Created local branch** `cherry-ddb0f26dc45-v4` for tracking
+6. **Force pushed** to remote `ci/cherry-ddb0f26dc45` to update the MR
+
+### Commits on the rebased branch (6 commits ahead of ci/master):
+1. `fabaed97412` - arm64: Convert core type check macros into inline functions
+2. `d646c30f0e2` - arm64: Add MIDR entries for Cortex-A57 and Cortex-A76
+3. `0133c5f8987` - arm64: renesas: Convert boards over to is_cortex_a() functions
+4. `831fd459b7c` - Merge branch 'master' of u-boot-sh (empty commit)
+5. `2a8dfb49519` - pickman: Record review handling for cherry-ddb0f26dc45
+6. `fb6b6dbed46` - pickman: Record review handling for cherry-ddb0f26dc45
+
+### Build result:
+- **OK** - sandbox board builds successfully
+
+### Suggested MR reply:
+```
+Rebased onto latest ci/master. Build verified OK.
+```
+
+---
+
+### Review: 2025-12-20
+
+Branch: cherry-ddb0f26dc45
+
+Comments addressed:
+
+
+### Conversation log
+The branch has 7 commits ahead of ci/master. Let me rebase onto the latest ci/master:
+
+The rebase was successful with no conflicts. Let me verify the result:
+
+The rebase completed successfully with 7 commits. Now let me run the build verification:
+
+Build passed. Now let me check for existing version branches and create the new one:
+
+There are v2, v3, and v4 already, so I need to create v5:
+
+The push failed due to stale info. Let me fetch and retry:
+
+Let me try a direct git push with force:
+
+Push successful. Let me verify the final state:
+
+## Summary
+
+**Rebase completed successfully** for MR !267 (branch: `cherry-ddb0f26dc45`)
+
+### What was done:
+1. **Checked out** the branch `cherry-ddb0f26dc45`
+2. **Rebased** onto latest `ci/master` using `git rebase --keep-empty ci/master` - no conflicts encountered
+3. **Verified build** - sandbox build completed successfully
+4. **Created local branch** `cherry-ddb0f26dc45-v5` for tracking
+5. **Force pushed** to remote `ci/cherry-ddb0f26dc45` to update the MR
+
+### Commits on the rebased branch (7 commits ahead of ci/master):
+1. `ff92c6c10b1` - arm64: Convert core type check macros into inline functions
+2. `a596758885e` - arm64: Add MIDR entries for Cortex-A57 and Cortex-A76
+3. `a9ade0292f2` - arm64: renesas: Convert boards over to is_cortex_a() functions
+4. `699fb7b375c` - Merge branch 'master' of u-boot-sh (empty commit)
+5. `7df3d5f40f7` - pickman: Record review handling for cherry-ddb0f26dc45
+6. `4daa4f6da0a` - pickman: Record review handling for cherry-ddb0f26dc45
+7. `add0fcb5259` - pickman: Record review handling for cherry-ddb0f26dc45
+
+### Build result:
+- **OK** - sandbox board builds successfully
+
+### Suggested MR reply:
+```
+Rebased onto latest ci/master. Build verified OK.
+```
+
+---
+

arch/arm/include/asm/armv8/cpu.h

@@ -3,11 +3,13 @@
  * Copyright 2018 NXP
  */
 
-#define MIDR_PARTNUM_CORTEX_A35	0xD04
+#define MIDR_PARTNUM_CORTEX_A35		0xD04
-#define MIDR_PARTNUM_CORTEX_A53	0xD03
+#define MIDR_PARTNUM_CORTEX_A53		0xD03
-#define MIDR_PARTNUM_CORTEX_A72	0xD08
+#define MIDR_PARTNUM_CORTEX_A57		0xD07
-#define MIDR_PARTNUM_SHIFT	0x4
+#define MIDR_PARTNUM_CORTEX_A72		0xD08
-#define MIDR_PARTNUM_MASK	(0xFFF << 0x4)
+#define MIDR_PARTNUM_CORTEX_A76		0xD0B
+#define MIDR_PARTNUM_SHIFT		0x4
+#define MIDR_PARTNUM_MASK		(0xFFF << MIDR_PARTNUM_SHIFT)
 
 static inline unsigned int read_midr(void)
 {
@@ -18,9 +20,17 @@ static inline unsigned int read_midr(void)
 	return val;
 }
 
-#define is_cortex_a35() (((read_midr() & MIDR_PARTNUM_MASK) >> \
+#define is_cortex_a(__n)					\
-			 MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A35)
+	static inline int is_cortex_a##__n(void)		\
-#define is_cortex_a53() (((read_midr() & MIDR_PARTNUM_MASK) >> \
+	{							\
-			 MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A53)
+		unsigned int midr = read_midr();		\
-#define is_cortex_a72() (((read_midr() & MIDR_PARTNUM_MASK) >>\
+		midr &= MIDR_PARTNUM_MASK;			\
-			 MIDR_PARTNUM_SHIFT) == MIDR_PARTNUM_CORTEX_A72)
+		midr >>= MIDR_PARTNUM_SHIFT;			\
+		return midr == MIDR_PARTNUM_CORTEX_A##__n;	\
+	}
+
+is_cortex_a(35)
+is_cortex_a(53)
+is_cortex_a(57)
+is_cortex_a(72)
+is_cortex_a(76)

board/hoperun/hihope-rzg2/hihope-rzg2.c

@@ -6,6 +6,7 @@
  * Copyright (C) 2021 Renesas Electronics Corporation
  */
 
+#include <asm/armv8/cpu.h>
 #include <asm/global_data.h>
 #include <asm/io.h>
 #include <asm/processor.h>
@@ -66,12 +67,7 @@ int board_init(void)
 
 void reset_cpu(void)
 {
-	unsigned long midr, cputype;
+	if (is_cortex_a53())
-
-	asm volatile("mrs %0, midr_el1" : "=r" (midr));
-	cputype = (midr >> 4) & 0xfff;
-
-	if (cputype == 0xd03)
 		writel(RST_CA53_CODE, RST_CA53RESCNT);
 	else
 		writel(RST_CA57_CODE, RST_CA57RESCNT);