Aswath Govindraju dd75927059 phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock ...

Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from
pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as a clock so that it's
possible to select one of these two inputs from device tree.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>

2022-02-08 11:00:03 -05:00

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allwinner

phy: Track power-on and init counts in uclass

2022-01-14 14:36:57 -05:00

cadence

phy: cadence: Sierra: Model PLL_CMNLC and PLL_CMNLC1 as a clock

2022-02-08 11:00:03 -05:00

marvell

phy: marvell: Remove unused function comphy_update_map()

2022-01-20 14:46:03 +01:00

rockchip

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socionext

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ti

phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC

2021-07-27 10:57:12 +05:30

bcm6318-usbh-phy.c

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bcm6348-usbh-phy.c

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bcm6358-usbh-phy.c

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bcm6368-usbh-phy.c

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Kconfig

phy: zynqmp: Add serdes/psgtr driver

2022-01-12 10:41:46 +01:00

keystone-usb-phy.c

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Makefile

phy: zynqmp: Add serdes/psgtr driver

2022-01-12 10:41:46 +01:00

meson-axg-mipi-dphy.c

phy: meson-axg-mipi: Rename "priv_auto_alloc_size" to "priv_auto"

2021-07-27 10:32:09 +02:00

meson-axg-mipi-pcie-analog.c

phy: meson-axg-mipi: Access parent ofnode through dev_ofnode()

2021-07-27 10:32:09 +02:00

meson-g12a-usb2.c

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meson-g12a-usb3-pcie.c

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meson-gxbb-usb2.c

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meson-gxl-usb2.c

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msm8916-usbh-phy.c

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mt76x8-usb-phy.c

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mt7620-usb-phy.c

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nop-phy.c

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omap-usb2-phy.c

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phy-ab8500-usb.c

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phy-bcm-sr-pcie.c

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phy-core-mipi-dphy.c

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phy-da8xx-usb.c

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phy-imx8mq-usb.c

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phy-mtk-tphy.c

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phy-qcom-ipq4019-usb.c

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phy-rcar-gen2.c

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phy-rcar-gen3.c

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phy-stm32-usbphyc.c

phy: stm32-usbphyc: stm32: usbphyc: add protection on phy sub-node

2021-10-08 08:19:59 +02:00

phy-ti-am654.c

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phy-uclass.c

phy: Track power-on and init counts in uclass

2022-01-14 14:36:57 -05:00

phy-zynqmp.c

phy: zynqmp: Add serdes/psgtr driver

2022-01-12 10:41:46 +01:00

sandbox-phy.c

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sti_usb_phy.c

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ti-pipe3-phy.c

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