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flesh out Etna skeleton a bit more

This commit is contained in:
Ash Wolf 2019-12-21 11:09:58 +00:00
parent 0ed437c6d3
commit 868112e9fc
5 changed files with 22 additions and 6 deletions
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2
WindCore/emu.cpp
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@ -6,7 +6,7 @@
#define INCLUDE_BANK1
Emu::Emu() {
Emu::Emu() : etna(this) {
}

2
WindCore/emu.h
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@ -5,6 +5,7 @@
#include <unordered_set>
class Emu {
public:
uint8_t ROM[0x1000000];
uint8_t MemoryBlockC0[0x800000];
uint8_t MemoryBlockC1[0x800000];
@ -12,6 +13,7 @@ class Emu {
uint8_t MemoryBlockD1[0x800000];
enum { MemoryBlockMask = 0x7FFFFF };
private:
uint32_t controlReg;
uint32_t translationTableBase;
uint32_t domainAccessControl;

13
WindCore/etna.cpp
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@ -1,4 +1,5 @@
#include "etna.h"
#include "emu.h"
#include <stdio.h>
#include <string.h>
@ -44,7 +45,9 @@ static const char *nameReg(uint32_t reg) {
}
Etna::Etna() {
Etna::Etna(Emu *owner) {
this->owner = owner;
for (int i = 0; i < 0x80; i++)
prom[i] = 0;
@ -77,9 +80,10 @@ Etna::Etna() {
uint32_t Etna::readReg8(uint32_t reg)
{
if (!promReadActive)
printf("ETNA readReg8: reg=%s\n", nameReg(reg));
printf("ETNA readReg8: reg=%s @ pc=%08x,lr=%08x\n", nameReg(reg), owner->getGPR(15) - 4, owner->getGPR(14));
switch (reg) {
case regSktVarA0: return 0; // will store some status flags
case regIntClear: return 0;
case regSktVarA0: return 1; // will store some status flags
case regSktVarA1: return 0; // will store some more status flags
case regWake1: return wake1;
case regWake2: return wake2;
@ -97,8 +101,9 @@ uint32_t Etna::readReg32(uint32_t reg)
void Etna::writeReg8(uint32_t reg, uint8_t value)
{
if (!promReadActive)
printf("ETNA writeReg8: reg=%s value=%02x\n", nameReg(reg), value);
printf("ETNA writeReg8: reg=%s value=%02x @ pc=%08x,lr=%08x\n", nameReg(reg), value, owner->getGPR(15) - 4, owner->getGPR(14));
switch (reg) {
case regIntClear: pendingInterrupts &= ~value; break;
case regWake1: wake1 = value; break;
case regWake2: wake2 = value; break;
}

7
WindCore/etna.h
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@ -1,16 +1,21 @@
#pragma once
#include <stdint.h>
class Emu;
class Etna {
uint8_t prom[0x80] = {};
uint16_t promReadAddress = 0, promReadValue = 0;
bool promReadActive = false;
int promAddressBitsReceived = 0;
uint8_t pendingInterrupts = 0, interruptMask = 0;
uint8_t wake1 = 0, wake2 = 0;
Emu *owner;
public:
Etna();
Etna(Emu *owner);
uint32_t readReg8(uint32_t reg);
uint32_t readReg32(uint32_t reg);

4
WindCore/wind_hw.h
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@ -1,5 +1,6 @@
#pragma once
#include "wind.h"
#include "arm.h"
#include <stdio.h>
struct Timer {
@ -113,6 +114,9 @@ struct UART {
if (reg == (UART0FCR & 0xFF)) {
return frameControl;
// UART0LCR
} else if (reg == (UART0FLG & 0xFF)) {
// we pretend we are never busy, never have full fifo
return FlagReceiveFifoEmpty;
} else {
printf("unhandled 32bit uart read %x at pc=%08x lr=%08x\n", reg, cpu->gprs[ARM_PC], cpu->gprs[ARM_LR]);
return 0xFFFFFFFF;