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clk: rockchip: rk3308: Support reading UART rate and clock registers

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Add support to read RK3308 registers used to configure UART clocks, and
thus to get UART rate and baudrate. This fixes clock_get_rate returning
error on serial device probing. Moreover, there is no need anymore to
use 'clock-frequency' property for UART nodes in *-u-boot.dtsi files
for all cases where UART is not inited by U-Boot proper or by SPL o by
TPL code but by a preliminary external boot phase (for Rock PI S, UART
is inited by external TPL).

Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Massimo Pegorer
2023-08-03 13:08:12 +02:00
committed by Kever Yang
parent e4c6ccc687
commit 0cd87aac5c
3 changed files with 74 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/dts/rk3308-rock-pi-s-u-boot.dtsi
View File

@@ -12,6 +12,4 @@
&uart0 {
bootph-all;
clock-frequency = <24000000>;
status = "okay";
};

15
arch/arm/include/asm/arch-rk3308/cru_rk3308.h
View File

@@ -189,6 +189,21 @@ enum {
DCLK_VOP_DIV_SHIFT = 0,
DCLK_VOP_DIV_MASK = 0xff,
/* CRU_CLKSEL_CON10 */
/* CRU_CLKSEL_CON13 */
/* CRU_CLKSEL_CON16 */
/* CRU_CLKSEL_CON19 */
/* CRU_CLKSEL_CON22 */
CLK_UART_PLL_SEL_SHIFT = 13,
CLK_UART_PLL_SEL_MASK = 0x7 << CLK_UART_PLL_SEL_SHIFT,
CLK_UART_PLL_SEL_DPLL = 0,
CLK_UART_PLL_SEL_VPLL0,
CLK_UART_PLL_SEL_VPLL1,
CLK_UART_PLL_SEL_480M,
CLK_UART_PLL_SEL_24M,
CLK_UART_DIV_CON_SHIFT = 0,
CLK_UART_DIV_CON_MASK = 0x1f << CLK_UART_DIV_CON_SHIFT,
/* CRU_CLK_SEL25_CON */
/* CRU_CLK_SEL26_CON */
/* CRU_CLK_SEL27_CON */

59
drivers/clk/rockchip/clk_rk3308.c
View File

@@ -451,6 +451,58 @@ static ulong rk3308_pwm_set_clk(struct clk *clk, uint hz)
return rk3308_pwm_get_clk(clk);
}
static ulong rk3308_uart_get_clk(struct clk *clk)
{
struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
struct rk3308_cru *cru = priv->cru;
u32 div, pll_sel, con, con_id, parent;
switch (clk->id) {
case SCLK_UART0:
con_id = 10;
break;
case SCLK_UART1:
con_id = 13;
break;
case SCLK_UART2:
con_id = 16;
break;
case SCLK_UART3:
con_id = 19;
break;
case SCLK_UART4:
con_id = 22;
break;
default:
printf("do not support this uart interface\n");
return -EINVAL;
}
con = readl(&cru->clksel_con[con_id]);
pll_sel = (con & CLK_UART_PLL_SEL_MASK) >> CLK_UART_PLL_SEL_SHIFT;
div = (con & CLK_UART_DIV_CON_MASK) >> CLK_UART_DIV_CON_SHIFT;
switch (pll_sel) {
case CLK_UART_PLL_SEL_DPLL:
parent = priv->dpll_hz;
break;
case CLK_UART_PLL_SEL_VPLL0:
parent = priv->vpll0_hz;
break;
case CLK_UART_PLL_SEL_VPLL1:
parent = priv->vpll0_hz;
break;
case CLK_UART_PLL_SEL_24M:
parent = OSC_HZ;
break;
default:
printf("do not support this uart pll sel\n");
return -EINVAL;
}
return DIV_TO_RATE(parent, div);
}
static ulong rk3308_vop_get_clk(struct clk *clk)
{
struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
@@ -813,6 +865,13 @@ static ulong rk3308_clk_get_rate(struct clk *clk)
case SCLK_EMMC_SAMPLE:
rate = rk3308_mmc_get_clk(clk);
break;
case SCLK_UART0:
case SCLK_UART1:
case SCLK_UART2:
case SCLK_UART3:
case SCLK_UART4:
rate = rk3308_uart_get_clk(clk);
break;
case SCLK_I2C0:
case SCLK_I2C1:
case SCLK_I2C2: