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mtd: spi-nor: Set ECC unit size to MTD writesize in Infineon SEMPER flashes

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The Infineon SEMPER NOR flash family uses 2-bit ECC by default with each
ECC block being 16 bytes. Under this scheme multi-pass programming to an
ECC block is not allowed. Set the writesize to make sure multi-pass
programming is not attempted on the flash.

Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
This commit is contained in:
Takahiro Kuwano
2024-10-15 13:08:36 +09:00
committed by Tom Rini
parent 20f1383bad
commit 10e75dd0bc
1 changed files with 14 additions and 0 deletions
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14
drivers/mtd/spi/spi-nor-core.c
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@@ -3855,6 +3855,13 @@ static void s25_late_init(struct spi_nor *nor,
struct spi_nor_flash_parameter *params)
{
nor->setup = s25_s28_setup;
/*
* Programming is supported only in 16-byte ECC data unit granularity.
* Byte-programming, bit-walking, or multiple program operations to the
* same ECC data unit without an erase are not allowed.
*/
params->writesize = 16;
}
static int s25_s28_post_bfpt_fixup(struct spi_nor *nor,
@@ -4019,6 +4026,13 @@ static void s28hx_t_late_init(struct spi_nor *nor,
{
nor->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable;
nor->setup = s25_s28_setup;
/*
* Programming is supported only in 16-byte ECC data unit granularity.
* Byte-programming, bit-walking, or multiple program operations to the
* same ECC data unit without an erase are not allowed.
*/
params->writesize = 16;
}
static void s28hx_t_post_sfdp_fixup(struct spi_nor *nor,