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spi: mxc_spi: use proper clock for SPI bus

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The mxc_get_clock function is around for compatibility with older
drivers that are not clock aware. In this case asking for the clk for
MXC_CSPI_CLK does not take into account there are multiple SPI busses on
modern IMX SoC's and it will return the clock for the first bus which
may not be used or configured.

In the case you are not using the first bus you will not get the proper
clock. Fix this by obtaining the clock rate from the bus clock.

This resolves an invalid SPI clock frequency configuration for SPI2 on a
board where SPI1 is not used.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
(cherry picked from commit f331967b3d)
This commit is contained in:
Tim Harvey
2024-12-18 11:42:24 -08:00
committed by Simon Glass
parent 874bc0dd1b
commit 23af5aaf59
1 changed files with 10 additions and 4 deletions
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14
drivers/spi/mxc_spi.c
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@@ -114,6 +114,9 @@ struct mxc_spi_slave {
u32 ctrl_reg;
#if defined(MXC_ECSPI)
u32 cfg_reg;
#endif
#if CONFIG_IS_ENABLED(CLK)
struct clk clk;
#endif
int gpio;
int ss_pol;
@@ -214,7 +217,11 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
#ifdef MXC_ECSPI
static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
{
#if CONFIG_IS_ENABLED(CLK)
u32 clk_src = clk_get_rate(&mxcs->clk);
#else
u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
#endif
s32 reg_ctrl, reg_config;
u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
u32 pre_div = 0, post_div = 0;
@@ -599,14 +606,13 @@ static int mxc_spi_probe(struct udevice *bus)
return -ENODEV;
#if CONFIG_IS_ENABLED(CLK)
struct clk clk;
ret = clk_get_by_index(bus, 0, &clk);
ret = clk_get_by_index(bus, 0, &mxcs->clk);
if (ret)
return ret;
clk_enable(&clk);
clk_enable(&mxcs->clk);
mxcs->max_hz = clk_get_rate(&clk);
mxcs->max_hz = clk_get_rate(&mxcs->clk);
#else
int node = dev_of_offset(bus);
const void *blob = gd->fdt_blob;