arm: Remove devkit3250 board
This board has not been converted to CONFIG_DM_I2C by the deadline. Remove it. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
@@ -6,9 +6,6 @@ config SYS_SOC
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choice
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prompt "NXP LPC32xx board select"
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config TARGET_DEVKIT3250
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bool "Timll DevKit3250"
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config TARGET_WORK_92105
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bool "Work Microwave Work_92105"
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@@ -17,7 +14,6 @@ config TARGET_EA_LPC3250DEVKITV2
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endchoice
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source "board/timll/devkit3250/Kconfig"
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source "board/work-microwave/work_92105/Kconfig"
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source "board/ea/ea-lpc3250devkitv2/Kconfig"
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@@ -1,12 +0,0 @@
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if TARGET_DEVKIT3250
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config SYS_BOARD
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default "devkit3250"
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config SYS_VENDOR
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default "timll"
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config SYS_CONFIG_NAME
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default "devkit3250"
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endif
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@@ -1,6 +0,0 @@
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DEVKIT3250 BOARD
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M: Vladimir Zapolskiy <vz@mleia.com>
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S: Maintained
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F: board/timll/devkit3250/
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F: include/configs/devkit3250.h
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F: configs/devkit3250_defconfig
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@@ -1,7 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
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# Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
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obj-y := devkit3250.o
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obj-$(CONFIG_SPL_BUILD) += devkit3250_spl.o
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@@ -1,83 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Embest/Timll DevKit3250 board support
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*
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* Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
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*/
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#include <config.h>
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#include <init.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/emc.h>
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#include <asm/arch/wdt.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct emc_regs *emc = (struct emc_regs *)EMC_BASE;
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static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
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static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
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void reset_periph(void)
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{
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/* This function resets peripherals by triggering RESOUT_N */
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setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
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writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl);
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udelay(300);
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writel(0, &wdt->mctrl);
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clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
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/* Such a long delay is needed to initialize SMSC phy */
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udelay(10000);
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}
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int board_early_init_f(void)
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{
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lpc32xx_uart_init(CONFIG_CONS_INDEX);
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lpc32xx_i2c_init(1);
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lpc32xx_i2c_init(2);
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lpc32xx_ssp_init();
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lpc32xx_mac_init();
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/*
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* nWP may be controlled by GPO19, but unpopulated by default R23
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* makes no sense to configure this GPIO level, nWP is always high
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*/
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lpc32xx_slc_nand_init();
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
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#ifdef CONFIG_SYS_FLASH_CFI
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/* Use 16-bit memory interface for NOR Flash */
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emc->stat[0].config = EMC_STAT_CONFIG_PB | EMC_STAT_CONFIG_16BIT;
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/* Change the NOR timings to optimum value to get maximum bandwidth */
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emc->stat[0].waitwen = EMC_STAT_WAITWEN(1);
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emc->stat[0].waitoen = EMC_STAT_WAITOEN(0);
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emc->stat[0].waitrd = EMC_STAT_WAITRD(12);
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emc->stat[0].waitpage = EMC_STAT_WAITPAGE(12);
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emc->stat[0].waitwr = EMC_STAT_WAITWR(5);
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emc->stat[0].waitturn = EMC_STAT_WAITTURN(2);
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#endif
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
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CFG_SYS_SDRAM_SIZE);
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return 0;
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}
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@@ -1,66 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Timll DevKit3250 board support, SPL board configuration
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*
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* (C) Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
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*/
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/emc.h>
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#include <asm/arch-lpc32xx/gpio.h>
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#include <spl.h>
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static struct gpio_regs *gpio = (struct gpio_regs *)GPIO_BASE;
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/*
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* SDRAM K4S561632N-LC60 settings are selected in assumption that
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* SDRAM clock may be set up to 166 MHz, however at the moment
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* it is 104 MHz. Most delay values are converted to be a multiple of
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* base clock, and precise pinned values are not needed here.
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*/
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struct emc_dram_settings dram_64mb = {
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.cmddelay = 0x0001C000,
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.config0 = 0x00005682,
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.rascas0 = 0x00000302,
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.rdconfig = 0x00000011, /* undocumented but crucial value */
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.trp = 83333333,
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.tras = 23809524,
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.tsrex = 12500000,
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.twr = 83000000, /* tWR = tRDL = 2 CLK */
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.trc = 15384616,
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.trfc = 15384616,
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.txsr = 12500000,
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.trrd = 1,
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.tmrd = 1,
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.tcdlr = 0,
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.refresh = 130000, /* 800 clock cycles */
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.mode = 0x00018000,
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.emode = 0x02000000,
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};
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void spl_board_init(void)
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{
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/* First of all silence buzzer controlled by GPO_20 */
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writel((1 << 20), &gpio->p3_outp_clr);
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lpc32xx_uart_init(CONFIG_CONS_INDEX);
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preloader_console_init();
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ddr_init(&dram_64mb);
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/*
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* NAND initialization is done by nand_init(),
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* here just enable NAND SLC clocks
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*/
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lpc32xx_slc_nand_init();
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}
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_NAND;
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}
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@@ -1,93 +0,0 @@
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CONFIG_ARM=y
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CONFIG_SKIP_LOWLEVEL_INIT=y
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CONFIG_SYS_ICACHE_OFF=y
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CONFIG_SYS_DCACHE_OFF=y
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CONFIG_ARCH_CPU_INIT=y
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CONFIG_ARCH_LPC32XX=y
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CONFIG_TEXT_BASE=0x83F00000
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CONFIG_SYS_MALLOC_LEN=0x100000
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CONFIG_SYS_MALLOC_F_LEN=0x400
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000f20
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CONFIG_ENV_SIZE=0x20000
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CONFIG_ENV_OFFSET=0xA0000
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CONFIG_SPL_TEXT_BASE=0x00000000
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CONFIG_SYS_MONITOR_LEN=393216
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CONFIG_SPL_SERIAL=y
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CONFIG_SPL_STACK=0xfff8
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CONFIG_SPL=y
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CONFIG_SYS_LOAD_ADDR=0x80008000
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CONFIG_BOOTDELAY=1
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttyS0,115200n8"
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CONFIG_USE_BOOTCOMMAND=y
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CONFIG_BOOTCOMMAND="dhcp; tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; setenv bootargs ${bootargs} ${nfsargs} ${userargs}; bootm ${loadaddr} - ${dtbaddr}"
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# CONFIG_DISPLAY_BOARDINFO is not set
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_SPL_MAX_SIZE=0x20000
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CONFIG_SPL_NO_BSS_LIMIT=y
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CONFIG_SPL_BOARD_INIT=y
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CONFIG_SPL_SYS_MALLOC_SIMPLE=y
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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CONFIG_SPL_NAND_SUPPORT=y
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CONFIG_SPL_NAND_RAW_ONLY=y
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CONFIG_SPL_NAND_DRIVERS=y
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CONFIG_SPL_NAND_ECC=y
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CONFIG_SPL_NAND_SOFTECC=y
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CONFIG_SPL_NAND_SIMPLE=y
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CONFIG_CMD_IMLS=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_NAND=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_DHCP=y
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CONFIG_SYS_DISABLE_AUTOLOAD=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_FAT=y
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CONFIG_CMD_JFFS2=y
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CONFIG_ENV_IS_IN_NAND=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_USE_BOOTFILE=y
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CONFIG_BOOTFILE="uImage"
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CONFIG_VERSION_VARIABLE=y
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CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
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CONFIG_DMA_LPC32XX=y
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CONFIG_LPC32XX_GPIO=y
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CONFIG_SYS_I2C_LEGACY=y
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CONFIG_SPL_SYS_I2C_LEGACY=y
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CONFIG_SYS_I2C_LPC32XX=y
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# CONFIG_MMC is not set
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CONFIG_MTD=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_FLASH_SHOW_PROGRESS=0
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CONFIG_SYS_FLASH_PROTECTION=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_SYS_MAX_FLASH_SECT=71
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CONFIG_MTD_RAW_NAND=y
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CONFIG_SYS_NAND_USE_FLASH_BBT=y
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CONFIG_NAND_LPC32XX_SLC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_PAGE_SIZE=0x800
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CONFIG_SYS_NAND_OOBSIZE=0x40
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# CONFIG_SYS_NAND_5_ADDR_CYCLE is not set
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CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
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CONFIG_SYS_NAND_U_BOOT_OFFS=0x40000
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CONFIG_PHYLIB=y
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CONFIG_PHY_ADDR_ENABLE=y
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CONFIG_PHY_ADDR=31
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CONFIG_PHY_SMSC=y
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CONFIG_RMII=y
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CONFIG_SPECIFY_CONSOLE_INDEX=y
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CONFIG_CONS_INDEX=5
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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CONFIG_USB=y
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CONFIG_SYS_USB_OHCI_SLOT_NAME="lpc32xx-ohci"
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CONFIG_USB_OHCI_LPC32XX=y
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CONFIG_OF_LIBFDT=y
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@@ -1,94 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Embest/Timll DevKit3250 board configuration file
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*
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* Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
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*/
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#ifndef __CONFIG_DEVKIT3250_H__
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#define __CONFIG_DEVKIT3250_H__
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/* SoC and board defines */
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#include <linux/sizes.h>
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#include <asm/arch/cpu.h>
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/*
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* Memory configurations
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*/
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#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE
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#define CFG_SYS_SDRAM_SIZE SZ_64M
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/*
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* DMA
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*/
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/*
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* GPIO
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*/
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/*
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* NOR Flash
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*/
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#define CFG_SYS_FLASH_BASE EMC_CS0_BASE
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#define CFG_SYS_FLASH_SIZE SZ_4M
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/*
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* NAND controller
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*/
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#define CFG_SYS_NAND_BASE SLC_NAND_BASE
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#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
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/*
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* NAND chip timings
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*/
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#define CFG_LPC32XX_NAND_SLC_WDR_CLKS 14
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#define CFG_LPC32XX_NAND_SLC_WWIDTH 66666666
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#define CFG_LPC32XX_NAND_SLC_WHOLD 200000000
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#define CFG_LPC32XX_NAND_SLC_WSETUP 50000000
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#define CFG_LPC32XX_NAND_SLC_RDR_CLKS 14
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#define CFG_LPC32XX_NAND_SLC_RWIDTH 66666666
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#define CFG_LPC32XX_NAND_SLC_RHOLD 200000000
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#define CFG_LPC32XX_NAND_SLC_RSETUP 50000000
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/*
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* USB
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*/
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#define CFG_USB_ISP1301_I2C_ADDR 0x2d
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/*
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* U-Boot General Configurations
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*/
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/*
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* Pass open firmware flat tree
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*/
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/*
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* Environment
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*/
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#define CFG_EXTRA_ENV_SETTINGS \
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"ethaddr=00:01:90:00:C0:81\0" \
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"dtbaddr=0x81000000\0" \
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"nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \
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"tftpdir=vladimir/oe/devkit3250\0" \
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"userargs=oops=panic\0"
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/*
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* U-Boot Commands
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*/
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/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_TEXT_BASE */
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#define CFG_SYS_NAND_U_BOOT_SIZE 0x60000
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#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
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#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
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/* See common/spl/spl.c spl_set_header_raw_uboot() */
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/*
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* Include SoC specific configuration
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*/
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#include <asm/arch/config.h>
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#endif /* __CONFIG_DEVKIT3250_H__*/
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Reference in New Issue
Block a user